An apparatus for performing level shift control in an electronic device includes an input stage positioned in a level shifter of the electronic device, and an output stage positioned in the level shifter and coupled to the input stage through a set of intermediate nodes. The input stage is arranged for receiving at least one input signal of the level shifter through at least one input terminal of the input stage and controlling voltage levels of the set of intermediate nodes according to the at least one input signal. The input stage includes a hybrid current control circuit coupled to the at least one input terminal and arranged for performing current control for the input stage. The hybrid current control circuit is equipped with multiple sets of parallel paths for controlling currents passing through the set of intermediate nodes, respectively, each set may include two or more paths in parallel.

An aspect relates to an apparatus including a first and second power rails; a first set of power switch cells coupled to the first and second power rails, the first set of power switch cells being cascaded from an output to an input of a control circuit; and a second set of power switch cells coupled to the first and second power rails, the second set of power switch cells being coupled to one of a pair of cells of the first set, the first output, and the first input of the control circuit. Another aspect relates to a method including propagating a control signal via a first set of cascaded power switch cells to sequentially couple a first power rail to a second power rail; and propagating the control signal via a second set of power switch cells coupled between a pair of cells of the first set.

The interface circuit includes a first transistor, a second transistor, a first switch, a first logic circuit and a second logic circuit. The first transistor is controlled by a enable signal. The second transistor is controlled by a first control signal. The first switch is coupled between a second end of the first transistor and the output end of the interface circuit, wherein the first switch is controlled by a second control signal. The first logic circuit generates the first control signal according to the enable signal and at least one indication signal. The second logic circuit generates the second control signal according to the first control signal and the enable signal.

A semiconductor structure is provided. The semiconductor structure includes a cell array having a plurality of rows. The cell array includes a plurality of first logic cells arranged in at least one first row, and a plurality of second logic cells arranged in at least one second row. The first logic cells share a first active region. Each of the second logic cells has a second active region, and the second active regions of two adjacent second logic cells are separated from each other by an isolation structure. The first logic cells of the first row are in contact with the second logic cells of the second row.

A CMOS output circuit includes a first P-MOSFET having a source connected to a power supply terminal, a drain connected to an output terminal, and a back gate connected to a first potential terminal; a first N-MOSEFET having a drain connected to the output terminal, a source connected to the ground terminal, and a back gate connected to a second potential terminal; a first potential switching portion arranged to switch whether to connect the first potential terminal to the power supply terminal or to the output terminal; a second potential switching portion arranged to switch whether to connect the second potential terminal to the ground terminal or to the output terminal; a first gate switching portion arranged to switch whether or not to short-circuit the gate of the first P-MOSFET to the first potential terminal; a second gate switching portion arranged to switch whether or not to short-circuit the gate of the first N-MOSFET to the second potential terminal; a first driver arranged to drive the gate of the first P-MOSFET in accordance with a first input signal; a second driver arranged to drive the gate of the first N-MOSFET in accordance with a second input signal; and a control portion arranged to control individual portions of the circuit when turning off both the first P-MOSFET and the first N-MOSFET, so as to connect the first potential terminal to one of the power supply terminal and the output terminal, which has a higher potential, to connect the second potential terminal to one of the ground terminal and the output terminal, which has a lower potential, to short-circuit the gate of the first P-MOSFET to the first potential terminal, and to short-circuit the gate of the first N-MOSFET to the second potential terminal.

A circuit for sensing local operating properties of an integrated circuit is disclosed. The circuit may include one or more sensor circuits configured to sense the local operating properties of the integrated circuit. The sensor circuits may receive a supply voltage with a magnitude in a limited range from a digital power supply that is different from the digital power supply that provides power to functional circuits in the integrated circuit. Level shifters may be coupled to the sensor circuits to shift output signals from the sensor circuits to levels that correspond to the digital power supply that provides power to functional circuits in the integrated circuit. Counters and a shift register may be coupled to the level shifters to receive the shifted output signals, the values of which may be used to determine the local operating properties of the integrated circuit as sensed by the sensor circuits.

According to an aspect, a current mode logic circuit comprise a first trim resistor and a second trim resistor connected to a supply voltage, a first transistor connected to an input voltage, a second transistor connected to an inverted input voltage and a third transistor and a fourth transistor connected to the first transistor and the second transistor, respectively, in a cascode manner in order to control magnitudes of an output voltage and an inverted output voltage of the current mode logic circuit.

A block of logic gates has MOS transistors whose body terminals are connected with a body voltage rail and whose source terminals are connected with a logic reference voltage rail. The logic reference voltage rail is connected to the body voltage rail via a resistor. The resistor creates a negative feedback loop for leakage currents that stabilizes a reverse body bias voltage and reduces the influence of temperature, voltage, and process variations.

The block may be NMOS, PMOS, or CMOS. In the case of CMOS, there are two body voltage rails, powered by a voltage source, two logic reference voltage rails, and two resistors. The reverse body bias voltages over the two resistors may be stabilized by decoupling capacitors. The two resistors may be trimmable. The resistors may be calibrated such that leakage currents are at a minimum value and the logic gates can switch just fast enough.

Various implementations described herein are directed to circuit. The circuit may include a first input stage having first devices and a first path for slow slew input detection. The circuit may include a second input stage having second devices and a second path for fast slew input detection. The circuit may include a separation stage that couples the second input stage to the first input stage during a first mode of operation so as to reduce power consumption of the circuit during slow slew input detection.

A semiconductor circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit determines a value of a first node based on a voltage level of a clock signal, and a voltage level of an enable signal or a voltage level of a scan enable signal. The second circuit determines a value of a second node based on the voltage levels of the first node and the clock signal. The third circuit determines a value of a third node based on a voltage level of the second node. The fourth circuit determines a value of a fourth node based on the voltage levels of the second node and the clock signal. The third circuit includes a first transistor and a second transistor connected in series with each other and gated to the voltage level of the second node to determine the value of the third node. The fourth circuit includes a third transistor that is gated to the voltage level of the clock signal to electrically connect the third node and the fourth node.