The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.

Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).

A digitally selectable power gate with thermometer-encoded upper bits may provide solutions for problems digital power gate-based regulators. These solutions may include the use of a fully binary power gate, either in structure or by local decoding of binary control signal to an addressable row-based power gate. This provides improved performance over a row-based code rotation, which is intended to avoid instantaneous overheating of power gate devices but may not mitigate aging effects. Another solution includes ganging a primary DLVR and one or more secondaries. The primary DLVR may include a voltage sense and active controller, which may forward its PG code to secondary instances. Therm and current sensor rotation may be performed locally at the secondaries and a current monitor data may be rolled up from all ganged DLVRs.

An overcurrent protection circuit and display drive device, comprising: when input current of a front end corresponding to a logic signal experiences overcurrent, preventing the input current of the front end experiencing overcurrent from being transmitted to a drive chip, thereby preventing damage to the drive chip.

A semiconductor device may include a division control circuit and a latch circuit. The division control circuit may be configured to divide an external clock to generate a first preliminary divided clock and a second preliminary divided clock. The division control circuit may be configured to output the first and second preliminary divided clocks or any one of the first and second preliminary divided clocks as first and second divided clocks. The latch circuit may be configured to latch an external control signal in response to the first and second divided clocks and configured to output latched signals as first and second latch control signals.

A bias voltage generator circuit may include a mode control circuit, a clock generator circuit coupled with the mode control unit and configured to generate a plurality of clock signals, and a charge pump circuit configured to receive the clock signals. The charge pump circuit may be coupled with the mode control circuit and operable to output selectable output voltages according to input from the mode control circuit. The output selectable voltages may depend upon the clock signals.

A clock circuit for clock gating using a cascaded clock gating control signal, including: a first B-latch accepting, as input, a clock gating control signal and enabled by a first clock signal; a second B-latch accepting, as input, an output from the first B-latch and enabled by a second clock signal; and a first logic outputting, based on the first B-latch, a first gated clock signal; and a second logic outputting, based on the second B-latch, a second gated clock signal.

A low clock power data-gated flip-flop is provided. The data-gated flip-flop includes an exclusive OR component including a first exclusive OR input, a second exclusive OR input, and a first exclusive OR output. The first exclusive OR input is configured to receive a data input to the data-gated flip-flop. The data-gated flip-flop includes a first latch including a first latch data input and a first latch reset input, the first exclusive OR output being coupled to the first latch data input and the first latch reset input. The data-gated flip-flop includes a second latch having a data output, the data output coupled to the second exclusive OR input.

Adaptively controlling drive strength of multiplexed power from supply power rails in a power multiplexing system to a powered circuit is disclosed. A power multiplexing circuit in the power multiplexing system includes a plurality of supply selection circuits (e.g., head switches) each coupled between a respective supply power rail and an output power rail coupled to the powered circuit. The power multiplexing circuit is configured to activate a selected supply selection circuit to switch coupling of an associated supply power rail to the output power rail to power the powered circuit. In one example, the supply selection circuits each include a plurality of power switch selection circuits coupled to an associated supply power rail. The power switch selection circuits are configured to be activated and deactivated by a control circuit to adjust drive strength of a multiplexed supply power rail based on operational conditions, which can account for performance variations.

A novel low power enable circuit is less sensitive to power supply variations while consuming less than 50 nA of supply current. The enable circuit includes a voltage clamp circuit which limits the supply level for a first inverter. The clamp circuit having a first input connected to a supply, a second input connected to chip enable, and a first output. The enable circuit further includes a first inverter having a third input connected to the chip enable, a fourth input connected to the first output of the clamp circuit, and a second output; a second inverter having a fifth input connected to the second output of the first inverter, a sixth input connected to the supply, and a third output; a memory element having a seventh input connected to the third output of the second inverter, an eighth input, and a fourth output; and a comparator having a ninth input connected to the chip enable, a tenth input connected to a reference signal, an eleventh input connected to the fourth output of the memory element, and a fifth output connected to the eighth input of the memory element.