A display is provided that includes an array of display pixels that receive data signals from display driver circuitry and that receive control signals from gate driver circuitry. The gate driver circuitry may include a chain of row driver circuits. Each row driver circuit in the chain of row driver circuits may include a master driver stage, a slave driver stage, and associated control circuitry configured to receive a clock signal and a pulse signal from a preceding row driver in the chain. The master driver stage may be biased using fixed nominal power supply voltages, whereas the slave driver stage may be biased using dynamically adjustable power supply voltages that are optionally reduced relative to that of the nominal power supply voltages. One or more of the master and slave driver stages may be a bootstrapping driver stage having a bootstrapping capacitor.

An adiabatic logic cell including a first MOS transistor coupling a node for applying a periodic variable supply voltage of the cell to a floating node for providing an output logic signal of the cell, wherein the first transistor is a dual-gate transistor including a front gate coupled to a node for applying an input logic signal of the cell, and a back gate coupled to a node for applying a first periodic variable bias voltage.

Methods and systems are provided for a security adaptive (SA) voltage converter that receives input power from a power source and provides power to a cryptographic system. The SA voltage converter triggers countermeasures against leakage power analysis (LPA) attacks that slow down an operating frequency of the cryptographic circuit. When an LPA attack is detected, a discharging resistor sinks redundant current to alter the signature of load power dissipation of at the input to the SA voltage converter system. The SA voltage converter includes a converter reshuffling converter. The power dissipation induced by the discharging resistor, as measured at the input received from the power source, is scrambled by the SA voltage converter to increase noise inserted into the input power and to alter the power profile that is measured for the cryptographic circuit.

An adiabatic logic cell including a first MOS transistor coupling a node for applying a periodic variable supply voltage of the cell to a floating node for providing an output logic signal of the cell, wherein the first transistor is a dual-gate transistor including a front gate coupled to a node for applying an input logic signal of the cell, and a back gate coupled to a node for applying a first periodic variable bias voltage.

A logic cell, including a first capacitor connected between an application node for applying a supply voltage of the cell and a floating node for providing an output logic signal of the cell, and, connected in parallel with the first capacitor, an association in series of a second capacitor and a first variable-resistance element, the first variable-resistance element including a control electrode connected to an application node for applying a first input logic signal of the cell.

A quantum charge parametron (QCP) includes a load capacitor; two quantum phase-slip junctions (QPSJs) coupled to each other through the load capacitor so as to define two charge islands, each charge island being located between the load capacitor and a respective one of the two QPSJs; at least one input voltage source coupled to the two QPSJs so that the two QPSJs, the load capacitor and the at least one input voltage source define a loop; and an excitation voltage source coupled to the two charge islands through first and second capacitors, respectively.

A memory cell in capacitive logic, including a bistable system including a fixed element and a mobile element capable of taking one or the other of two stable positions with respect to the fixed element; a read device including a variable-capacitance capacitor including a first fixed electrode and a second mobile electrode rigidly fixed to the mobile element; and an electrically controllable write device for placing the mobile element in one or the other of its two stable positions.

An adiabatic logic-in-memory based complementary metal-oxide-semiconductor/magnetic-tunnel-junction (ALiM CMOS/MTJ) circuit utilizes an adiabatic logic based pre-charged sense amplifier (PCSA) to recover energy from its output load capacitors. The ALiM CMOS/MTJ includes a non-volatile magnetic-tunnel-junction (MTJ) based memory. The ALiM CMOS/MTJ also includes a dual rail complementary metal-oxide-semiconductor (CMOS) logic that performs logic operations in association with the MTJ, and thereby generates logic outputs based on logic inputs. The ALiM CMOS/MTJ also includes the adiabatic PCSA, which is operatively coupled to the dual rail CMOS logic. The adiabatic logic based PCSA includes PCSA circuitry for which an input is a multi-phase power clock, and a charge recovery circuit having the output load capacitors. The charge recovery circuit is operatively coupled to the PCSA circuitry such that the ALiM CMOS/MTJ circuit uses the power clock to recover energy from the output load capacitors.

An integrated circuit includes a highest class core circuit that has a positive power supply terminal connected to a positive power supply terminal of an external power source, and is configured to receive a first supply voltage which is at least a portion of a an input supply voltage that is provided from the external power source based on an operation throughput; and a lowest class core circuit that has a positive power supply terminal connected to a negative power supply terminal of an adjacent upper class core circuit, has a negative power supply terminal connected to a negative power supply terminal of the external power source, and is configured to receive a second supply voltage which is at least a portion of a part of the input supply voltage that excludes the first supply voltage.

Electronic devices employing adiabatic logic circuits with wireless charging are disclosed. In one aspect, an electronic device is provided. The electronic device includes a power circuit employing an alternating current (AC) coupler circuit configured to receive a wireless AC signal and generate a wired AC signal based on the wireless AC signal. The power circuit includes a power output configured to provide an AC power signal based on the wired AC signal generated by the AC coupler circuit. The AC power signal is generated based on the wireless charging capability of the AC coupler circuit. The electronic device employs a digital logic system that includes a power rail electrically coupled to an adiabatic logic circuit. The AC power signal is provided to the power rail to provide power to the adiabatic logic circuit. Wirelessly charging the adiabatic logic circuit consumes less power than conventional non-wireless charging circuitry.