A high-voltage output driver (1) for a sensor device (100) with reverse current blocking comprises a supply node (SN) to apply a supply voltage (VHV) and an output node (OP) to provide an output signal (OS) of the high-voltage output driver (1). The high-voltage output driver (1) comprises a driver transistor (MP0) being disposed between the supply node (SN) and the output node (OP). The high-voltage output driver (1) further comprises a bulk control circuit (20) to apply a bulk control voltage (Vwell) to a bulk node (BMP0) of the driver transistor (MP0), and a gate control circuit (30) to apply a gate control voltage (GCV) to the gate node (GMP0) of the driver transistor (MP0).

Systems and methods related to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation are provided. A system includes a plurality of devices configured to operate in a cryogenic environment, where a first distribution of a threshold voltage associated with the plurality of devices has a first value indicative of a measure of spread of the threshold voltage. The system further includes control logic, coupled to each of the plurality of devices, configured to modify a threshold voltage associated with each of the plurality of devices such that the first distribution is changed to a second distribution having a second value of the measure of spread of the threshold voltage representing a lower variation among threshold voltages of the plurality of devices.

A multi-level signal transmitter includes a voltage selection circuit, which is configured to select one amongst a plurality of driving voltages, which have different voltage levels, in response to input data including at least two bits of data therein. A driver circuit is also provided, which is configured to generate an output data signal as a multi-level signal, in response to the selected one of the plurality of driving voltages. This selected signal is provided as a body bias voltage to at least one transistor within the driver circuit. This driver circuit may include a totem-pole arrangement of first and second MOS transistors having respective first and second body bias regions therein, and at least one of the first and second body bias regions may be responsive to the selected one of the plurality of driving voltages.

The invention relates to a high-voltage voltage level converter for matching of the components of electronic systems containing multiple power sources. In particular, the high-voltage voltage level converter includes seven P-type field-effect transistors and seven N-type field-effect transistors, the signal input terminal (IN), the inputs of reference source voltages ⅔VDD) and (⅓VDD), inverted output, high-level source voltage terminals (VCC) and (VDD), and low-level source voltage terminal (VSS).

An amplifier device includes an amplifier circuitry, a controller circuitry, and an offset cancellation circuitry. The amplifier circuitry is configured to amplify a first input signal and a second input signal, in order to generate a first output signal and a second output signal. The controller circuitry is configured to generate a first control signal and a second control signal according to the first output signal and the second output signal. The offset cancellation circuitry is configured to provide a negative capacitor to the amplifier circuitry, and to adjust at least one current flowing through a circuit, which provides the negative capacitor, of the offset cancellation circuitry according to the first control signal and the second control signal, in order to cancel an offset of the amplifier circuitry.

Multiple polymorphic Multi-Threshold NULL Convention Logic gates that exhibit one function under a higher supply voltage, and the other function under a lower supply voltage and asynchronous polymorphic circuits able to implement two distinctive functionalities controlled by the supply voltage.

Described is a high speed, low power level shifter circuit which includes a level shifter coupled to a sensing circuit. The level shifter includes a pair of source transistors, a pair of input transistors, and a pair of switching circuits connected between the source transistors and the input transistors. The sensing circuit turns off a switching circuit on an active side of the level shifter based on detecting that an output voltage of the level shifter has completed a voltage level transition from a first logic level voltage to a second logic level voltage. An open circuit is established on the active side and turns off the pair of source transistors. The other switching circuit is turned on. Static current flow on the active side of the level shifter is stopped and the output voltage is latched to a voltage representative of the second logic level voltage.

In an embodiment, a voltage comparator includes: a first switch having a conduction terminal coupled to an internal node that is coupled to an output of the voltage comparator; a current source; a capacitor; and a second switch connected in parallel with the capacitor, wherein the current source, the capacitor, and the first switch are coupled in series.

The invention relates to computer technology and can be used for creation of fast-response high-voltage voltage level converters, in particular, for matching of the components of electronic systems containing multiple power sources. The achieved technical result is the increase of response rate of CMOS digital level shift circuit. For this purpose, the circuit of the high-voltage voltage level converter contains seven P-type FETs (1-7) and seven N-type FETs (8-14), the signal input terminal IN, the inputs of reference source voltages ⅔VDD and ⅓VDD, inverted output OUT, high-level source voltage terminals VCC and VDD, and low-level source voltage terminal VSS.

An input/output circuit includes a logic unit configured to generate a first signal and a second signal based on data and a first control signal, a driver including a first PMOS transistor having a first gate, a first source that receives a first voltage from a first voltage source, and a first drain, and a first NMOS transistor having a second gate that receives the second signal, a second source that receives a second voltage from a second voltage source less than the first voltage, and a second drain connected to the first drain, a gate-tracking circuit configured to receive the first signal and transfer the received first signal to the first gate of the first PMOS transistor based on a second control signal, and an input/output terminal connected to the first drain and the second drain.