A latch circuit includes an AND-NOR gate, a NAND gate, and a NOR gate. The AND-NOR gate includes a first AND-input configured to receive input data and a second AND-input coupled to an output of the NAND gate. The AND-NOR gate includes a NOR-input coupled to an output of the NOR gate, and an output configured to generate output data. The NAND gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a clock signal. The NOR gate includes a first input coupled to the output of the AND-NOR gate and a second input configured to receive a complementary clock signal. During a first half clock cycle, the AND-NOR gate passes the data from the input to the output. During a second half clock cycle, the feedback configuration of the AND-NOR gate and the NOR gate latches the data.

An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

A semiconductor device includes a plurality of semiconductor dies spaced from each other in a vertical direction and an inter-die interface that electrically connects the plurality of semiconductor dies. The plurality of semiconductor dies includes a transceiver circuit that transmits and receives a clock signal and a data signal through the inter-die interface, and a delay control circuit located on a signal transmission path of one signal among the clock signal and the data signal for delaying the one signal. At least one semiconductor die among the plurality of semiconductor dies is a logic die. The hybrid semiconductor device according to an embodiment of the present disclosure may reduce skew between dies.

A sequential circuit includes a data input terminal, a data path, and a redundant feedback loop. The data input terminal receives input data. The data path is connected to the data input terminal and transmits the input data to a data output terminal based on a first clock signal and a second clock signal. The redundant feedback loop is connected to the first data path and stores first data based on at least one of the first or second clock signals when the first data is equal to second data. The first data corresponds to the input data. The second clock signal is a delayed signal of the first clock signal. The second data is delayed data of the first data.

According to one embodiment of the present disclosure, a circuit includes a Correlated Electron Switch (CES) element and a programming circuit. The CES element includes a first input. The first input of the CES element is coupled to an input signal to be monitored. The CES element is programmed in a first impedance state. The programming circuit coupled to the CES element is configured to switch the CES element from the first impedance state to a second impedance state in response to a voltage transition on the input signal. The voltage transition indicates a fault event. The output element coupled to the first input of the CES element determines that the transition has occurred responsive to the CES element switching to the second impedance state.

A method for implementing a programmable critical delay path measurement in-line with the critical path logic cells. Additionally, the delay measurement creates a code to be used with a programmable DLL which indicates the delay of the measured critical path. This code can also be used by an off line First Fail Circuit which can mimic the delay of the critical path and give an indication of the critical path delay. The target of this invention is to create a method to optimize the required operating voltage of an integrated circuit per specific speed requirement, overcoming different process variations, temperatures changes and in die variations.

One embodiment describes a reciprocal quantum logic (RQL) receiver system. The RQL system is configured to convert a serial input data stream provided from a serial data transmitter into an RQL data stream. The RQL receiver system includes a sampling controller configured to oversample the serial input data stream via a plurality of samples over each sampling window of an RQL clock signal to determine a transition sample corresponding to a transition in a digital value of the serial input data stream in a given one sampling window of the RQL clock signal. The RQL receiver system can be further configured to capture the digital value of the serial input data stream via a capture sample that is a predetermined number of samples subsequent to the transition sample in each sampling window of the RQL clock signal.

An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.

A semiconductor apparatus may include a noise determination circuit, a strobe signal control circuit, and a reception circuit. The noise determination circuit may sense and determine noise of a reference voltage, and generate an up control signal and a down control signal. The strobe signal control circuit may adjust a transition timing of a strobe signal in response to the up control signal and the down control signal, and output a control strobe signal. The reception circuit may generate internal data signal in response to external data signal, the reference voltage, and the control strobe signal.

An electronic circuit includes: a first logic circuit coupled to a first input line and a first output line; a second logic circuit coupled to a second input line and a second output line; a first line pattern coupled to the first output line and including an input line different from the second input line; and a second line pattern coupled to the second output line and different from the first input line, wherein at least a part of the first output line, the first line pattern, the second output line, or the second line pattern has a folded shape or a circular shape.