An integrated circuit delay cell includes an input circuit to establish a current level in the circuit, a switch configured to control an on/off time of a delay circuit, a delay circuit including at least one current starved stage configured to mirror the current level, the delay circuit configured to control a speed of a rise and/or fall time of an output signal, and a glitch discharging circuit connected to the delay circuit configured to tolerate and discharge unwanted charge of the delay circuit.

An integrated circuit delay cell includes an input circuit to establish a current level in the circuit, a switch configured to control an on/off time of a delay circuit, a delay circuit including at least one current starved stage configured to mirror the current level, the delay circuit configured to control a speed of a rise and/or fall time of an output signal, and a glitch discharging circuit connected to the delay circuit configured to tolerate and discharge unwanted charge of the delay circuit.

Disclosed aspects relate to a clock distribution network of a synchronous logic device. The synchronous logic device has sub-circuits having different clock domains. The clock domains form a hierarchical structure. The clock distribution network has a clock source to provide a global clock signal. A programmable delay line associated with a sub-circuit generates a local clock signal for the sub-circuit by delaying the signal. A global skew control circuit can manage clock skew between the local clock signals. The global skew control circuit may adjust a delay, determine initial operations for the delay lines, verify whether it is possible to perform the initial operations, and perform a correction operation. The correction operation can include correcting the control commands such that the corrected commands lead to the same change of skew adjustment between the local clocks.

A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.

Embodiments include a memory device with an improved calibration circuit. Memory device input/output pins include delay lines for adjusting the delay in each memory input/output signal path. The delay adjustment circuitry includes digital delay lines for adjusting this delay. Further, each digital delay line is calibrated via a digital delay line locked loop which enables adjustment of the delay through the digital delay line in fractions of a unit interval across variations due to differences in manufacturing process, operating voltage, and operating temperature. The disclosed techniques calibrate the digital delay lines by measuring both the high phase and the low phase of the clock signal. As a result, the disclosed techniques compensate for duty cycle distortion by combining the calibration results from both phases of the clock signal. The disclosed techniques thereby result in lower calibration error relative to approaches that measure only one phase of the clock signal.

A buffer circuit includes an input terminal configured to receive an input signal, an output terminal, an inverter, and a resistor-capacitor (RC) circuit coupled in series with the inverter between the input terminal and the output terminal. The RC circuit includes an NMOS transistor coupled between an RC circuit output terminal and a reference node, a resistor coupled between the RC circuit output terminal and a power supply node, and a capacitor coupled between the RC circuit output terminal and one of the power supply node or the reference node, and the inverter and the RC circuit are configured to generate an output signal at the output terminal based on the input signal.

Methods and apparatuses pertaining to hold-time compensation using free metal segments or other electrically-conductive segments of an IC are described. An integrated circuit (IC) having free segment hold-time compensation may include a monolithic semiconductor substrate which has a first device and a second device disposed thereon. In addition, the IC may include an electrical node electrically connecting the first and second devices. The electrical node may include one or more electrically-conductive elements that contribute to a total capacitance at the electrical node such that the total capacitance at the electrical node has a value that fulfills a hold-time requirement at the electrical node.

A skew compensation circuit includes a skew detection circuit configured to generate skew detection signals by detecting a skew characteristic of a basic logic element constituting a semiconductor apparatus, a skew compensation signal generation circuit configured to generate a skew compensation signal by comparing the skew detection signals and a plurality of reference voltages, a variable delay circuit configured to generate a compensation signal by delaying an input signal by a delay time varied according to the skew compensation signal, and a reference voltage generation circuit configured to generate the plurality of reference voltages of which offset components are compensated for according to variations of a temperature and an external voltage.

A delay circuit includes an electronic transmission element with a first input and a first output. The first input is coupled to the first output by two first switches wired in parallel. The first switches each have a control input, a second input and a second output. The second input is coupled to the second output by two second switches wired in parallel. The circuit further includes an input circuit to receive an input signal and feed the input signal to one of the transmission element inputs and feed the inverted input signal to the other of the transmission element inputs, and an output circuit. The output circuit is configured such that the output signal only changes in the case of a change in the input signal if the change in the input signal has brought about a change both at the first output and at the second output.

A distributed data acquisition system comprising multiple, physically unconnected, data acquisition units that can be in wireless communication with a remote host, timestamps measurement data with sub-microsecond time base accuracy of sampling clock relative to an absolute timeframe. Each unit has a GPS receiver for deriving an absolute time. An analog-to-digital converter samples measurement data using a sampling clock. A hardware logic circuit, such as a field programmable gate array, associates batches of the measurement data with corresponding timestamps representing the current absolute time. A time offset bias may be compensated by a comparison of timestamps with nominal time based on start time and nominal sampling rate. Additionally, the sampling clock may be synchronized using time pulses from the GPS receiver. An initial start of ADC sampling by all data acquisition units may be also synchronized.