Techniques to compensate non-radiation hardened components for changes in performance that result from exposure to radiation. The techniques of this disclosure apply a predetermined bias signal to a representative non-radiation hardened component while a system is in use. The system determines whether there is a performance change in characteristics, such as voltage response, frequency response, gain, or other characteristics. The system may determine a compensation factor that may restore the desired signal output from the component. The system may compensate a second identical component that is in use in the system with the compensation factor. The component receiving the predetermined bias signal acts as a characterization dosimeter of the component in use in the system. A number of radiation vulnerable components may be characterized simultaneously with exact representative parts. The system may compensate identical component in use in the system with the appropriate compensation factor for each.

A latchup detector includes a level shifter and a comparator. The level shifter is electrically coupled to a voltage supply rail to receive as inputs a regulator output voltage and a target supply voltage. The level shifter includes a first level-shifter circuit that lowers the regulator output voltage to a first voltage and a second level-shifter circuit that lowers the target supply voltage to a second voltage. The comparator receives as inputs the first and second voltages. The comparator produces a first output voltage when the difference between the first and second voltages is greater than or equal to a predetermined voltage difference and a second output voltage when the difference between the first and second voltages is less than the predetermined voltage difference. The first output voltage can correspond to a latchup event.

This invention comprises a new way to connect a control, CK, and data, D, signal into a basic cross-coupled INV pair, and into certain other basic sequential logic circuits, to control the writing in of a new data value, D, into the sequential logic circuit cell. The invention concerns logic circuit in complementary metal-oxide-semiconductor (CMOS) technology. It connects additional p-type and n-type MOSFET devices in a novel manner to accomplish the desired control functions.

Provided is a Precision Voltage Reference (PVR). In one example, the PVR includes a resonator having an oscillation frequency, the resonator including a first proof-mass, a first forcer located adjacent a first side of the first proof-mass, and a second forcer located adjacent a second side of the first proof-mass. The PVR may include control circuitry configured to generate a reference voltage based on the oscillation frequency of the resonator, at least one converter configured to receive the reference voltage from the control circuitry, provide a first bias voltage to the first forcer based on the reference voltage, provide a second bias voltage to the second forcer based on the reference voltage, and periodically alter a polarity of the first and second bias voltages to drive the oscillation frequency to match a reference frequency, and an output configured to provide the reference voltage as a voltage reference signal.

A break-before-make (BB4M) circuit topology is disclosed for use with a multiplexer that eliminates shoot-through current between analog inputs and also between an analog input and analog output. The BB4M circuit generates a pulse that disables an existing selected channel before enabling a newly selected channel or gate driver, and is suitable for use in high-radiation or outer space operating environments.

An electric device, which includes a first switch-unit providing a first internal circuit signal, a first delay circuit unit outputting a second internal circuit signal which is generated by delaying the first internal circuit signal, a first AND logic outputting a first repair-signal generated by a logical AND operation between the first internal circuit signal and the second internal circuit signal, a first OR logic outputting a second repair-signal generated by a logical OR operation between the first internal circuit signal and the second internal circuit signal, and a second switch-unit selecting one of the first repair-signal and the second repair-signal according to a third internal circuit signal generated by an operation including a logical AND operation between the first repair-signal and the second repair-signal and providing the selected one as an output signal through an output terminal, is released.

An electric device, which includes a first switch-unit providing a first internal circuit signal, a first delay circuit unit outputting a second internal circuit signal which is generated by delaying the first internal circuit signal, a first AND logic outputting a first repair-signal generated by a logical AND operation between the first internal circuit signal and the second internal circuit signal, a first OR logic outputting a second repair-signal generated by a logical OR operation between the first internal circuit signal and the second internal circuit signal, and a second switch-unit selecting one of the first repair-signal and the second repair-signal according to a third internal circuit signal generated by an operation including a logical AND operation between the first repair-signal and the second repair-signal and providing the selected one as an output signal through an output terminal, is released.

The present disclosure describes various aspects of complementary 2(N)-bit redundancy for single event upset (SEU) prevention. In some aspects, an integrated circuit includes a data storage element to store a data value, another data storage element to store a complementary data value, a multi-bit data storage element (e.g., a 2-bit storage element) to store both the data value and the complementary data value, and voting logic that may enable a complementary data storage scheme with inter-circuit redundancy to prevent SEU. Additionally, the voting logic of the integrated circuit may enable detection and correction of data value errors and/or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected.

A system for detecting radiation events, having: a test memory with memory blocks; a controller having controller memory; an integrated circuit (IC) array having IC chains, wherein each of the IC chains has a plurality of IC elements that is response to and generates a voltage when exposed to a radiation event; a dosimeter configured to record an accumulated amount of radiation exposure to the system, wherein the controller is configured to perform steps of: initializing the test memory, the IC array and the dosimeter; monitoring for an unexpected signal from an IC chain and for unexpected data in a memory block of the test memory; and identifying the radiation event upon one or more of receiving the unexpected signal and identifying unexpected data in a memory block of the test memory.

A break-before-make (BB4M) circuit topology is disclosed for use with a multiplexer that eliminates shoot-through current between analog inputs and also between an analog input and analog output. The BB4M circuit generates a pulse that disables an existing selected channel before enabling a newly selected channel or gate driver, and is suitable for use in high-radiation or outer space operating environments.