The present disclosure provides a PUF circuit including a first array including at least one physically unclonable function (PUF) cell, a second array including at least one PUF cell, and a controller which selects a first PUF cell from the first array and selects a second PUF cell from the second array and generates unique information represented by the first PUF cell and the second PUF cell based on a first output voltage output by the first PUF cell and a second output voltage output by the second PUF cell.

A voltage tracking circuit is provided and includes first and second P-type transistors and a voltage reducing circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The voltage reducing circuit is coupled between the first voltage terminal and the gate of the first P-type transistor. The voltage reducing circuit reduces a first voltage at the first voltage terminal by a modulation voltage to generate a control voltage and provides the control voltage to the gate of the first P-type transistor. The gate of the second P-type transistor is coupled to the first voltage terminal, and the drain thereof is coupled to a second voltage terminal. The source of the first P-type transistor and the source of the second P-type transistor are coupled to the output terminal of the voltage tracking circuit. The output voltage is generated at the output terminal.

An apparatus includes a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer and a fourth signal through a fourth main buffer, a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer, and a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.

An apparatus includes a primary processor and a secondary processor configured to receive a first signal, a second signal and a plurality of input signals, and perform same operations as each other based on the first signal, the second signal and the plurality of input signals, a comparison circuit configured to receive output signals of the primary processor and the secondary processor, and detect a lockstep mismatch between the primary processor and the secondary processor based on the output signals, a fault capturing circuit configured to receive the first signal and the second signal, and capture a fault signal generated by the comparison circuit, and a first glitch absorption device configured to receive the first signal and the second signal, and absorb glitches fed into the first glitch absorption device.

An overvoltage protection device including an output stage, a first switch and a first load providing circuit is provided. The output stage has a first input terminal to receive a first signal, and generates an output signal at an output terminal of the output stage according to the first signal. A first terminal of the first switch is coupled to the first input terminal of the output stage, and a control terminal of the first switch receives a second signal. The first signal is the delayed second signal. The first load providing circuit is coupled to a second terminal of the first switch. The first load providing circuit provides an impedance to the first input terminal when the first switch is turned on.

Systems and methods for reducing jitter due to power supply noise in an integrated circuit by drawing additional current. The additional current causes the total current to generally have a frequency higher than a resonant frequency of the integrated circuit and/or a power distribution network of the integrated circuit. A power distribution network may supply power to components of an integrated circuit, and data driver circuitry may draw first current to drive a serial data signal generated from a parallel data signal. Compensation circuitry may receive the parallel data signal and draw second current at times when the compensation circuitry determines data driver circuitry is not drawing the first current based on the parallel data signal, thereby causing a net of the first and second current to be higher than a resonant frequency range of the integrated circuit device and/or a component of the integrated circuit device.

A voltage controlled oscillator is provided. The voltage controlled oscillator includes a current controlled oscillator, a voltage to current conversion circuit and a noise cancellation circuit. The current controlled oscillator is configured to receive a bias current and generate an oscillating signal with an oscillating frequency according to the bias current. The voltage to current conversion circuit is coupled to a power supply voltage and configured to generate a supply current according to an input voltage. The noise cancellation circuit is configured to receive a bias voltage and the supply current from the voltage to current conversion circuit, and configured to generate a noise cancellation current in response to power supply voltage variation and cancel the noise cancellation current from the supply current to generate the bias current. The bias voltage of the noise cancellation circuit is coupled to an internal voltage of the voltage to current conversion circuit.

A method and apparatus for mitigating electromagnetic noise in an electronic device. The method includes generating a trigger clock signal at a first frequency, and generating a second clock signal at a second frequency. The second frequency is higher than the first frequency. The method also includes receiving an input signal with a converter circuit, detecting an event based on the trigger clock signal, and predicting a time for a conversion of the input signal based on the detected event. The method further includes blanking the second clock signal for a predetermined period based on the predicted time for a conversion.

A circuit includes a first delay filter, a first comparator, an inverter, a second delay filter, a second comparator, an OR gate, and a latch. A first delay filter input is coupled to an inverter input. The first comparator has a first comparator input coupled to a first delay filter output and a second comparator input. The second delay filter has an input coupled to an inverter output. The second comparator has a third comparator input coupled to a second delay filter output, and a fourth comparator input coupled to the second comparator input. The OR gate has an input coupled to a first comparator output and another input coupled to a second comparator output. The latch has a clock input coupled to an OR gate output and a latch input coupled to the inverter input. A latch output provides a deglitched signal.

An integrated circuit (IC) can include multiple power domains that are served by a common power source. In an example, a first IC power rail can be coupled to the source and a first consumer circuit. A second IC power rail can be coupled to a second consumer circuit. The second IC power rail can receive a filtered power signal from an isolation module that is coupled between the first and second power rails. In an example, an isolation module includes an integrated inductor and a capacitor (e.g., a land-side capacitor). The integrated inductor can optionally include multiple spaced apart conductive layers that are electrically coupled. The integrated inductor can optionally include a series of conductive traces and plated through holes or vias that together provide a current path with multiple turns.