Circuits and methods for switching between an internal clock and an external clock without causing an interruption or an artifact in the switched clock signal are disclosed. To achieve this, the internal clock signal is synchronized with the external clock signal prior to switching. The synchronization may be accomplished using two possible clock-synchronization methods: a first method that passively waits for the clocks to synchronize over time and a second that adjusts a period of the internal clock signal to actively synchronize the clocks. The method selected for use requires the fewest clock cycles to reach synchronization, which is determined by a frequency difference between the two clock frequencies. After clock-synchronization, the output clock signal spectrum will be substantially the same before and after switching between the clock signals, and therefore is suitable for use with spread spectrum clocks.

This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (P.sub.RO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (P.sub.RST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (V.sub.RB1, V.sub.PB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

A synchronizer circuit includes a first synchronizer having a first input for receiving a signal associated with a first clock signal, a second input for receiving a second clock signal, and an output for providing a synchronizer circuit output signal; a second synchronizer having a first input for receiving the signal associated with the first clock signal, a second input for receiving the second clock signal, and an output; a detection stage having a first input coupled to the output of the first synchronizer and to the output of the second synchronizer, a second input for receiving the second clock signal, and an output; and a fault output stage having a first input coupled to the detection stage, a second input for receiving the second clock signal, and an output for providing a fault output signal.

The invention relates to a communication interface between a control unit and an electric load unit, particularly a load unit having a pump motor in a motor vehicle, wherein the control unit is designed as a transmitter and/or receiver, wherein the load unit is designed as a receiver and/or transmitter and wherein the communication between the transmitter and the receiver takes place via a signal line by means of a pulse-width-modulated signal. In this case, there is provision for the signal line to be connected to a constant current source and for the transmitter to be designed to modulate the flow of current through the signal line by means of pulse-width modulation. The invention further relates to a method for operating such a communication interface.

System for reducing pattern-dependent inter-symbol interference (ISI) are described. These systems may be implemented using complementary metal-oxide-semiconductor (CMOS) transistors. These systems are designed to clamp the voltage propagating along the datapath to a value that is a fraction of the supply voltage. Furthermore, these systems are designed to reduce the time constant of the datapath. One such system comprises a source including a digital-to-analog converter (DAC) and a destination comprising an analog-to-digital converter (ADC). A circuit disposed along the data path from the DAC to the ADC is configured to receive a supply voltage, receive an input signal from the DAC, and produce an output signal based on the input signal by clamping the output signal to a voltage that is a fraction of the supply voltage.

A signal driver circuit includes a first inversion driver, a second inversion driver and an emphasis driver. The first inversion driver is configured to receive a first signal, and output a second signal by inversion-driving the first signal. The second inversion driver is configured to receive the second signal, and output a third signal by inversion-driving the second signal. The emphasis driver is configured to receive the third signal, inversion-drive the third signal, and combine the inversion-driven signal to the first signal.

A signal driver circuit includes a first inversion driver, a second inversion driver and an emphasis driver. The first inversion driver is configured to receive a first signal, and output a second signal by inversion-driving the first signal. The second inversion driver is configured to receive the second signal, and output a third signal by inversion-driving the second signal. The emphasis driver is configured to receive the third signal, inversion-drive the third signal, and combine the inversion-driven signal to the first signal.

System for reducing pattern-dependent inter-symbol interference (ISI) are described. These systems may be implemented using complementary metal-oxide-semiconductor (CMOS) transistors. These systems are designed to clamp the voltage propagating along the datapath to a value that is a fraction of the supply voltage. Furthermore, these systems are designed to reduce the time constant of the datapath. One such system comprises a source including a digital-to-analog converter (DAC) and a destination comprising an analog-to-digital converter (ADC). A circuit disposed along the data path from the DAC to the ADC is configured to receive a supply voltage, receive an input signal from the DAC, and produce an output signal based on the input signal by clamping the output signal to a voltage that is a fraction of the supply voltage.

A method is provided for controlling communication in wireless charging. The method comprises: controlling wireless power transfer with a device; receiving a communication signal from the device; generating a jamming signal based on the communication signal from the device; and applying the jamming signal to the communication signal to obtain a jammed communication signal. A device is also provided for controlling communication in wireless charging. The device is configured to control wireless power transfer and receive a communication signal. The device comprises: a jamming circuit configured to generate a jamming signal based on the received communication signal, wherein the device is further configured to apply the jamming signal to the received communication signal to obtain a jammed communication signal.