An extended General Purpose Input/Output (eGPIO) scheme is disclosed. In some implementations, an input/output (I/O) boundary scan cell comprises an output path to route output signals from a first voltage domain and signals from a second voltage domain to an I/O pad operating in a pad voltage domain, the output path having a first level shifter to up shift the output signals from the first voltage domain or the second voltage domain to the pad voltage domain; an input path to receive input signals from the I/O pad, the input path having a second level shifter to down shift the input signals from the pad voltage domain to the second voltage domain; and test logic to test signals in the first voltage domain and the second voltage domain.

A noise cancelling circuit includes: a first parallel-serial conversion circuit which converts inputted 2N-bit parallel data into serial data; an inverting circuit which inverts one of odd-numbered bits and even-numbered bits included in the inputted 2N-bit parallel data; a second parallel-serial conversion circuit which converts, into serial data, parallel data outputted by the inverting circuit and parallel data of the other one of the odd-numbered bits and the even-numbered bits included in the inputted 2N-bit parallel data which were not inverted; a first buffer which receives output data of the first parallel-serial conversion circuit; and a second buffer which receives output data of the second parallel-serial conversion circuit.

To provide a novel shift register. Transistors 101 to 104 are provided. A first terminal of the transistor 101 is connected to a wiring 111 and a second terminal of the transistor 101 is connected to a wiring 112. A first terminal of the transistor 102 is connected to a wiring 113 and a second terminal of the transistor 102 is connected to the wiring 112. A first terminal of the transistor 103 is connected to the wiring 113 and a gate of the transistor 103 is connected to the wiring 111 or a wiring 119. A first terminal of the transistor 104 is connected to a second terminal of the transistor 103, a second terminal of the transistor 104 is connected to a gate of the transistor 101, and a gate of the transistor 104 is connected to a gate of the transistor 102.

A qubit circuit and a method for topological protection of a qubit circuit are described. The circuit comprises a plurality of physical superconducting qubits and a plurality of coupling devices interleaved between pairs of the physical superconducting qubits. The coupling devices are tunable to operate the qubit circuit either in a topological regime or as a series of individual physical qubits. At least two superconducting loops, each one threadable by an external flux, are part of the qubit circuit.

A qubit circuit and a method for topological protection of a qubit circuit are described. The circuit comprises a plurality of physical superconducting qubits and a plurality of coupling devices interleaved between pairs of the physical superconducting qubits. The coupling devices are tunable to operate the qubit circuit either in a topological regime or as a series of individual physical qubits. At least two superconducting loops, each one threadable by an external flux, are part of the qubit circuit.

A noise cancelling circuit includes: a first parallel-serial conversion circuit which converts inputted 2N-bit parallel data into serial data; an inverting circuit which inverts one of odd-numbered bits and even-numbered bits included in the inputted 2N-bit parallel data; a second parallel-serial conversion circuit which converts, into serial data, parallel data outputted by the inverting circuit and parallel data of the other one of the odd-numbered bits and the even-numbered bits included in the inputted 2N-bit parallel data which were not inverted; a first buffer which receives output data of the first parallel-serial conversion circuit; and a second buffer which receives output data of the second parallel-serial conversion circuit.

An anti-interference integrated circuit (IC) is adapted for avoiding an error in a frequency pulse caused by the interference of an adjacent IC. The anti-interference IC outputs a first time signal, and the adjacent IC outputs a second time signal. The anti-interference IC includes: a logic circuit, an adder, and a comparator. The logic circuit outputs a gate pulse according to a sequence of the second time signal. The adder adds the first time signal and the gate pulse. The comparator outputs the frequency pulse according to a signal adding result, where the period of the frequency pulse is the same as the period of the first time signal.

This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (P.sub.RO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (P.sub.RST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (V.sub.PB1, V.sub.PB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

An integrated circuit (IC) can include multiple power domains that are served by a common power source. In an example, a first IC power rail can be coupled to the source and a first consumer circuit. A second IC power rail can be coupled to a second consumer circuit. The second IC power rail can receive a filtered power signal from an isolation module that is coupled between the first and second power rails. In an example, an isolation module includes an integrated inductor and a capacitor (e.g., a land-side capacitor). The integrated inductor can optionally include multiple spaced apart conductive layers that are electrically coupled. The integrated inductor can optionally include a series of conductive traces and plated through holes or vias that together provide a current path with multiple turns.

An anti-interference integrated circuit (IC) is adapted for avoiding an error in a frequency pulse caused by the interference of an adjacent IC. The anti-interference IC outputs a first time signal, and the adjacent IC outputs a second time signal. The anti-interference IC includes: a logic circuit, an adder, and a comparator. The logic circuit outputs a gate pulse according to a sequence of the second time signal. The adder adds the first time signal and the gate pulse. The comparator outputs the frequency pulse according to a signal adding result, where the period of the frequency pulse is the same as the period of the first time signal.