This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (P.sub.RO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (P.sub.RST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (V.sub.PB1, V.sub.PB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (P.sub.RO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (P.sub.RST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (V.sub.RB1, V.sub.PB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

An embodiment level converter circuit is configured to receive, as a current supply, a current proportional to temperature.

Some embodiments include apparatuses and methods using a supply node to receive a die voltage; a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal; a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.

A circuit includes a voltage bus, a load, a plurality of switches, a controller, an encoder, a first switch group, and a second switch group. The first switch group is electrically connected between the voltage bus and the load. The second switch group is also electrically connected between the voltage bus and the load. The controller provides a first output signal indicating a required number of switches to be turned on to meet a power demand of the load. The encoder is configured to select a first combination of on/off states of the first switch group and the second switch group based on (i) the first output signal from the controller and (ii) a second combination of on/off states of the first switch group and the second switch group, and in response to selecting the first combination, transmit a switch signal to effect the first combination.

An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.

During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly addressing this droop so as to reduce the probability of circuit timing failures. This problem is addressed by provided an apparatus that is configured to detect the droop and react to mitigate the droop. The apparatus includes a frequency divider that is configured to receive an output of a clock signal generator (e.g. a phase locked loop) and produce an output signal in which a predefined fraction of the clock pulses in the output of the clock signal generator are removed from the output signal. By reducing the frequency of the clock signal in this way (as may be understood by examining equation 3) V.sub.DD is increased, hence mitigating the voltage droop. This technique provides a fast throttling mechanism that prevents excessive V.sub.DD droop across the processor.

Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.

A circuit arrangement includes two switching group series circuits of switch assemblies, switch-mode power supply units, and two capacitor bridges connecting the switching group series circuits. Each switch assembly has a parallel circuit of a semiconductor switch and a freewheeling diode as well as a driver for actuating the semiconductor switch. Each switch-mode power supply unit is associated with a switch pair of semiconductor switches and supplies the drivers of both semiconductor switches of the switch pair with energy. Each switch pair is formed by a semiconductor switch of a first switching group series circuit and a semiconductor switch of a second switching group series circuit. A power convertor module having the circuit arrangement is also provided.