Embodiments of an sequential state element (SSE) capable of providing triple modular redundant (TMR) correction is disclosed. The SSE has a setup stage and a feedback stage. The setup stage is configured to generate an output bit signal having an output bit state while a clock signal is in the first clock state. The setup stage also generates a feedback input bit signal as feedback of the output bit state. However, the feedback stage is capable of providing TMR correction without this feedback signal. Instead, the feedback stage utilizes the second feedback input bit signal and a third feedback input bit signal from two other SSEs. Since TMR correction can be provided with just the second feedback input bit signal and the third feedback input bit signal, the power and area consumed by the SSE is reduced.

An interference-suppression circuit produces an interference-reduced signal from output signals of a plurality of redundant functional blocks. A first extreme-value determination unit determines the specific output signal that represents a first extreme value from the output signals of the functional blocks. A processing unit offsets the output signals of the plurality of functional blocks against one another in such a manner that the interference-reduced signal is determined. The processing unit omits from consideration the first extreme value in determining the interference-reduced signal.

Embodiments of an sequential state element (SSE) capable of providing triple modular redundant (TMR) correction is disclosed. The SSE has a setup stage and a feedback stage. The setup stage is configured to generate an output bit signal having an output bit state while a clock signal is in the first clock state. The setup stage also generates a feedback input bit signal as feedback of the output bit state. However, the feedback stage is capable of providing TMR correction without this feedback signal. Instead, the feedback stage utilizes the second feedback input bit signal and a third feedback input bit signal from two other SSEs. Since TMR correction can be provided with just the second feedback input bit signal and the third feedback input bit signal, the power and area consumed by the SSE is reduced.

A fingerprint information detection circuit comprises an amplification unit, a source follower unit, a reset unit, and a feedback unit. The amplification unit is coupled to the source follower unit. The reset unit is coupled to both the feedback unit and the amplification unit. The feedback unit and the amplification unit are coupled. The reset unit includes a first transistor and a reset transistor, wherein source and drain electrodes of the first transistor are coupled, wherein one of source and drain electrodes of the reset transistor is coupled to the source and drain electrodes of the first transistor.

A reconfigurable circuit suitable for a redundant circuit of a storage device is provided. A programmable logic element (PLE) includes k logic circuits (e.g., XNOR circuits), k configuration memories (CM), and another logic circuit (e.g., an AND circuit) to which the outputs of the k logic circuits are input. The output of the AND circuit represents whether k input data of the PLE all correspond to configuration data stored in the k CMs. For example, when the address of a defective block in the storage device is stored in the CM and address data of the storage device the access of which is requested is input to the PLE, whether the defective block is accessible can be determined from the output of the AND circuit.

The present invention relates to a chip design and discloses a fingerprint information detection circuit. The invention includes a reset unit, a feedback unit, an amplification unit and a source follower unit; the reset unit is connected to the feedback unit and amplification unit, while the feedback unit is connected to the amplification unit, and the amplification unit is connected to the source follower unit; when the reset transistor built-into the reset unit is on, it stores an electric charge, and resets the feedback unit; when the reset transistor is off, the stored electric charge is injected into the feedback unit and amplification unit; the feedback unit receives the electric charge, and outputs the second voltage signal generated when it detects fingerprints to the source follower unit; the amplification unit amplifies the received signal and outputs it to the source follower unit; the source follower unit receives the signal, performs voltage level shifting before outputting the first voltage signal that carries the detected fingerprint information. The present invention enables the circuit to use a reduced chip area, hence, saving the cost of the chip.

An apparatus including one or more relays and a fault detector is disclosed. The one or more relays are coupled to a load. The fault detector is coupled with the one or more relays and receives at least one control signal. The fault detector includes a sensor to detect electricity flowing through the load and generate a detection signal. Based on a comparison of the control signal and the detection signal, the fault detector generates a fault signal indicative of whether a relay is functional or faulty.

Systems or methods of the present disclosure may provide a programmable logic device including multiple logic array blocks each having multiple programmable elements. The multiple logic array blocks are arranged in multiple rows that are segmented into multiple segments. The programmable logic device also includes repair circuitry disposed between the multiple segments. The repair circuitry remaps logic within a first segment of the multiple segments when a first logic array block of the multiple logic array blocks has failed. Moreover, the first segment includes the first logic array block.

An apparatus for detecting faults in devices, the apparatus comprising a first input for receiving a first control signal for controlling a switch, a first output for providing the first control signal to the switch, a sensor to detect a presence and an absence of electricity flowing through a load controlled by the switch to generate a detection signal, and circuitry configured to compare the detection signal and the first control signal and generate a fault signal indicating whether a fault is detected. When a logic level of the detection signal is the same as a logic level of the first control signal, the fault signal indicates that the fault is not detected. When the logic level of the detection signal is different from the logic level of the first control signal, the fault signal indicates that the fault is not detected.

A power management device is provided including a circuit module configured to provide a set of voltage biases for one or more target devices. The circuit module includes a set of first transistors of a first type and disposed in a doped region, a set of well ties disposed in the doped region and located a predetermined distance from the set of first transistors, a set of second transistors of a second type and disposed outside the doped region, and a set of substrate ties disposed between the doped region and the set of second transistors.