A buffer circuit includes a first MOSFET including a first source electrode, a first gate electrode, and a first drain electrode, and a second MOSFET, which includes a second source electrode, a second gate electrode, and a second drain electrode, and is same in polarity as the first MOSFET, and the first gate electrode and the second gate electrode are electrically connected to each other.

A safety switching device for fail-safely disconnecting an electrical load has an input part for receiving a safety-relevant input signal, a logic part for processing the at least one safety-relevant input signal, and an output part. The output part has a relay coil and four relay contacts. The first and second relay contacts are arranged electrically in series with one another. The third and fourth relay contacts are also arranged electrically in series with one another. The first and the third relay contacts are mechanically coupled to each other and form a first group of positively driven relay contacts. The second and the fourth relay contacts are mechanically coupled to each other and form a second group of positively driven relay contacts. The logic part redundantly controls the first and the second groups of positively driven relay contacts to selectively allow, or to interrupt in a fail-safe manner, a current flow to the electrical load, depending on the safety-relevant input signal. The relay coil is electromagnetically coupled to the first and second groups of positively driven relay contacts so that the logic part can control the relay contacts together via a single relay coil.

A reconfigurable circuit suitable for a redundant circuit of a storage device is provided. A programmable logic element (PLE) includes k logic circuits (e.g., XNOR circuits), k configuration memories (CM), and another logic circuit (e.g., an AND circuit) to which the outputs of the k logic circuits are input. The output of the AND circuit represents whether k input data of the PLE all correspond to configuration data stored in the k CMs. For example, when the address of a defective block in the storage device is stored in the CM and address data of the storage device the access of which is requested is input to the PLE, whether the defective block is accessible can be determined from the output of the AND circuit.

Methods, systems, and apparatus for detecting single event effects. The system includes a first-modulus digital logic unit and a second-modulus digital logic unit each configured to reduce one or more operands by a respective modulus, apply an arithmetic compute logic to the reduced operands to produce a respective compute output, and reduce the respective compute output by their respective modulus. The system includes a kernel digital logic unit configured to apply the arithmetic compute logic to the operands to produce a kernel compute output, output the kernel compute output reduced by the first modulus, and output the kernel compute output reduced by the second modulus. The system includes a detector configured to detect a single event effect based on the reduced first compute output, the kernel compute output reduced by the first modulus, the reduced second compute output, and the kernel compute output reduced by the second modulus.

A circuit structure and a method for supressing single event transients (SETs) or glitches in digital electronic circuits are provided. The circuit includes a first input which receives an output of a digital electronic circuit and a second input which receives a redundant or duplicated output of the digital electronic circuit. The circuit includes only four two-input gates of two different kinds selected from AND, OR, NAND and NOR gates. The four two-input gates being arranged so that a final circuit output is impervious to a change in a logic level of only the first input or only the second input, and the final circuit output is equivalent to the logic level of the first and second inputs when the logic level of the first and second inputs match.

Various implementations described herein are directed to a device having a scan chain that receives a multi-bit input, provides a multi-bit output, and provides a multi-bit multiplexer output based on the multi-bit input and the multi-bit output. The device may have an error-bit generator that receives the multi-bit multiplexer output, receives a portion of the multi-bit input, receives a portion of the multi-bit output, and provides an error-bit output based on the multi-bit multiplexer output, the portion of the multi-bit input, and the portion of the multi-bit output.

A buffer circuit includes a first MOSFET including a first source electrode, a first gate electrode, and a first drain electrode, and a second MOSFET, which includes a second source electrode, a second gate electrode, and a second drain electrode, and is same in polarity as the first MOSFET, and the first gate electrode and the second gate electrode are electrically connected to each other.

Safety and/or reliability may he improved in industrial control systems by optimally utilizing integrated circuit elements to reduce the amount of components required and to provide cross monitoring. In one aspect, circuitry that is part of an Integrated Circuit (IC) for controlling a first channel may also be used to monitor and provide safe operation for circuitry for controlling a second channel, and the circuitry for controlling the second channel may similarly be used to monitor and provide safe operation for the circuitry controlling the first channel. Circuitry may include a windowed watchdog circuit which may be used to monitor various events of the other circuitry, and safe operation may be provided by removing power from the other circuitry to provide a safe state.

A buffer circuit includes a first MOSFET including a first source electrode, a first gate electrode, and a first drain electrode, and a second MOSFET, which includes a second source electrode, a second gate electrode, and a second drain electrode, and is same in polarity as the first MOSFET, and the first gate electrode and the second gate electrode are electrically connected to each other.

A reconfigurable circuit suitable for a redundant circuit of a storage device is provided. A programmable logic element (PLE) includes k logic circuits (e.g., XNOR circuits), k configuration memories (CM), and another logic circuit (e.g., an AND circuit) to which the outputs of the k logic circuits are input. The output of the AND circuit represents whether k input data of the PLE all correspond to configuration data stored in the k CMs. For example, when the address of a defective block in the storage device is stored in the CM and address data of the storage device the access of which is requested is input to the PLE, whether the defective block is accessible can be determined from the output of the AND circuit.