An analog multiplexer core circuit (120A) includes a differential pair (121) that includes two transistors (Q1, Q2), a differential pair (122) that includes two transistors (Q3, Q4), a differential pair (123) that includes two transistors (Q5, Q6), and a constant current source (124) that causes a current (I.sub.EE) to flow. This analog multiplexer core circuit (120A) time-multiplexes two analog signals (Ain1, Ain2) and outputs a time-multiplexed analog signal (Aout). Each emitter resistor (R.sub.EA1, R.sub.EA2, R.sub.EA3, R.sub.EA4) is connected to a corresponding one of the transistors (Q1, Q2, Q3, Q4). At this time, a relation of R.sub.EA.Math.I.sub.EEthe amplitude of an input analog signal is satisfied. As a result, linearity of response can be ensured by expanding the linear response input range of the differential pairs (121, 122).

A data communication system has a first data communication circuit for outputting a clock signal to a clock signal line, receiving data input from a data signal line, and outputting data as open drain output to the data signal line, a second data communication circuit for receiving input of a clock signal from the clock signal line, receiving input of data from the data signal line, and outputting data as open drain output to the data signal line, a first pull-up resistor connected between the data signal line and the wiring of a power supply potential, a second pull-up resistor for selectively pulling up the data signal line, and a pull-up control circuit that is connected to the second pull-up resistor, and strengthens pull-up of the data signal line at least in response to a clock signal.

The present disclosure relates to methods and circuits to lowering the signal range of switching or logic circuits below supply range. The circuits may have one or more stages. The supply levels can be set individually for each stage. This may realize amplifiers/attenuators, both digitally and analogically controlled, based on progression and/or modulation in the supply range from stage to stage. A chain of stages can provide the desired power gain by setting the supply progression according to the nature of the incoming signals. The signal levels are lowered by generic device networks comprising voltage sources providing voltages independent of currents flowing through. Decoupling the signal amplitude from DC biasing allows for the signal swing to be lower than threshold voltages of the active devices.

A combinational circuit (e.g., multiplexer or demultiplexer) comprises a sub-circuit that comprises first and second current paths from an input of the combinational circuit to an output of the combinational circuit, such that substantially all input current at the input of the combinational circuit is conducted by the sub-circuit via the first and second current paths to the output of the combinational circuit. The first current path comprises a first inductor and a first switch; and the second current path comprises a second inductor and a second switch. The first inductor is part of an output LC transmission line of the sub-circuit; the second inductor is part of an input LC transmission line of the sub-circuit; and the first and second inductors are sized such that parasitic capacitances of the first and second switches are substantially absorbed by the input and output LC transmission lines.

A transmitter controls the fall time on an open-drain link including multiple components. The transmitter includes an input driver to receive data and transmit the data on the open-drain link, thereby activating the open-drain link. The transmitter also includes a feedback mechanism to keep track of a pad when the open-drain link is activated and to determine when the pad reaches a predetermined amount of a supply voltage. When the pad reaches the predetermined amount of a supply voltage, the feedback mechanism triggers an appropriate main pull-down driver to control the fall time.

An on-board device installed in a vehicle and is provided with an input circuit including an input end into which an input voltage is entered, and a drive power supply circuit that outputs a drive voltage to the input circuit. The input circuit includes a PNP bipolar transistor, a pull-up circuit, a second pull-up resistance, and a base resistance. The pull-up circuit includes a pull-up power supply, a first pull-up resistance, and a second diode with an anode facing the first pull-up resistance, which are connected in series and are provided between a base of the PNP bipolar transistor and the input end. The second pull-up resistance is provided between the base of the PNP bipolar transistor and the drive power supply circuit. The base resistance is provided between the base of the PNP bipolar transistor and the second pull-up resistance.

A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.