Disclosed is technology that is driven using a positive feedback loop of a feedback field-effect transistor and is capable of performing a logic-in memory function. The logic-in-memory inverter includes a metal oxide semiconductor field-effect transistor, and a feedback field-effect transistor in which a drain region of a nanostructure is connected in series to a drain region of the metal oxide semiconductor field-effect transistor, wherein the logic-in-memory inverter performs a logical operation is performed based on an output voltage V.sub.OUT that changes depending on a level of an input voltage V.sub.IN that is input to a gate electrode of the feedback field-effect transistor and a gate electrode of the metal oxide semiconductor field-effect transistor while a source voltage V.sub.SS is input to a source region of the nanostructure and a drain voltage V.sub.DD is input to a source region of the metal oxide semiconductor field-effect transistor.

A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

A driving adjustment circuit and an electronic device are provided. The driving adjustment circuit includes a first NOT gate module, second NOT gate module and third NOT gate module sequentially connected. An input terminal of the first NOT gate module and an output terminal of the third NOT gate module are connected to a signal terminal. The first NOT gate module acquires a to-be-driven signal from the signal terminal and perform a NOT operation on the to-be-driven signal to obtain a first adjustment signal. The second NOT gate module receives the first adjustment signal and performing the NOT operation on the first adjustment signal to obtain a second adjustment signal, when the driving adjustment circuit is in an ON state. The third NOT gate module receives the second adjustment signal and perform voltage adjustment processing on the to-be-driven signal at the signal terminal according to the second adjustment signal.

Disclosed is technology that is driven using a positive feedback loop of a feedback field-effect transistor and is capable of performing a logic-in memory function. The logic-in-memory inverter includes a metal oxide semiconductor field-effect transistor, and a feedback field-effect transistor in which a drain region of a nanostructure is connected in series to a drain region of the metal oxide semiconductor field-effect transistor, wherein the logic-in-memory inverter performs a logical operation is performed based on an output voltage V.sub.OUT that changes depending on a level of an input voltage V.sub.IN that is input to a gate electrode of the feedback field-effect transistor and a gate electrode of the metal oxide semiconductor field-effect transistor while a source voltage V.sub.SS is input to a source region of the nanostructure and a drain voltage V.sub.DD is input to a source region of the metal oxide semiconductor field-effect transistor.

An example adapter device includes a host-side connector to connect to a host device, the host-side connector including a host-side electrical contact to connect to a corresponding electrical contact of the host device. The adapter device further includes a storage-side connector to connect to storage devices operable under different protocols, the storage-side connector including a storage-side electrical contact to connect to a connected storage device. The adapter device further includes a circuit to apply a bias voltage to the host-side electrical contact. The host-side electrical contact is to provide a protocol-indicating voltage to indicate to the host device a protocol of the connected storage device. The protocol-indicating voltage is dependent on the connected storage device's influence on the bias voltage.

The present application provides a storage system including a data port. The data port includes a data output unit. The data output unit includes: a pull-up unit having a control terminal, a first terminal and a second terminal, a first input signal being inputted to the control terminal, the first terminal being electrically connected to a power supply, the second terminal being connected to an output terminal of the data output unit, and the pull-up unit being a first NMOS transistor; and a pull-down unit having a control terminal, a first terminal and a second terminal, a second input signal being inputted to the control terminal, the first terminal being electrically connected to a ground terminal, and the second terminal being connected to the output terminal of the data output unit.

A memory device and operating method of the memory device are provided. The memory device comprises a memory cell storing data based on a first voltage, a row decoder selecting a wordline of the memory cell based on the first voltage, and a wordline predecoder configured to generate a “predec” signal, which is for generating a wordline voltage to be provided to the row decoder. The wordline predecoder is driven by the first voltage and a second voltage, which is different from the first voltage, receives a row address signal, associated with selecting the wordline, and an internal clock signal associated with adjusting operating timings of elements included in the memory device. The wordline predecoder performs a NAND operation on the row address signal and the internal clock signal, and provides the “predec” signal generated based on a result of the NAND operation to the row decoder.

A repeater for open-drain bus communication and a system including the same is provided. The repeater includes at least one repeating unit having an A-side terminal connected to an A-side open-drain bus, and a B-side terminal electrically connected to a B-side open-drain bus. The repeater has a first mode to receive a signal at the A-side and to produce a signal at the B-side. The repeating unit includes a B-side accelerator element connected to the B-side terminal. The repeating unit when in a first mode includes a first control unit to, control the B-side accelerator element to pull up a voltage at the B-side when the voltage at the A-side surpasses a first threshold voltage during a rising edge of the voltage, and to subsequently control the B-side accelerator element to stop pulling up the voltage at the B-side when the voltage at the B-side surpasses a second threshold voltage.

A repeater for open-drain bus communication and a system including the same is provided. The bus repeater includes an A-to-B buffer to receive the signal at the A-side terminal and to produce a first buffered signal, a B-side pull-down control unit to produce a first control signal based on the received first buffered signal, and a B-side pull-down element to pull down the voltage at the B-side terminal based on the first control signal. The B-side pull-down element includes a B-side pull-down transistor that is arranged in between the B-side terminal and a B-side ground reference terminal. The first control signal controls a voltage at the control terminal of the B-side pull-down transistor. The B-side pull-down control unit includes a B-side comparing unit to compare the voltage at the B-side terminal to a first reference voltage, and to generate the first control signal based on a result of the comparison.