Various embodiments relate to a transmit driver circuit, including: a first node connected to a first differential output; a first transistor connected in series with a first resistor, wherein the series connected first transistor and first resistor are connected between a source voltage and the first node; a second transistor connected in series with a second resistor, wherein the series connected second transistor and second resistor are connected between the first node and a ground; a second node connected to a second differential output; a third transistor connected in series with a third resistor, wherein the series connected third transistor and third resistor are connected between the source voltage and the second node; a fourth transistor connected in series with a fourth resistor, wherein the series connected fourth transistor and fourth resistor are connected between the second node and the ground; a first differential input connected to the gate of the first transistor and the gate of the fourth transistor; and a second differential input connected to the gate of the second transistor and the gate of the third transistor, wherein the first transistor, second transistor, third transistor, and fourth transistor are NMOS transistors.

The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.

Systems and methods for routing communication among a plurality of devices are described. In an example, a controller can detect a communication initiated from a first device to a target device among a second device and a third device. The controller can identify the second device as the target device. The controller can, in response to identifying the second device as the target device, activate a direct communication path between the first device and the second device to allow the first device to communicate with the second device using direct communication mode. The controller can, in response to identifying the second device as the target device, activate redriver path between the first device and the third device to allow the first device to communicate with the third device using redriver mode.

A power domain change circuit includes an input circuit and an output circuit. The input circuit is suitable for operating in a first power domain and generating first and second intermediate processing signals. The output circuit is suitable for operating in a second power domain and generating a final output signal by averaging and combining transition jitter components of the first and second intermediate processing signals.

A level shift circuit includes: a first transistor connected to ground and having a control terminal; a second transistor connected to the ground and having a control terminal connected to the a terminal of the first transistor; a pull-up circuit connected to a power source and also connected to the first terminal of the first transistor, and having a current mirror circuit constituted by two transistors; a third transistor having a first terminal connected to the first terminal of the first transistor, a second terminal connected to the power source, and a control terminal connected to a first terminal of the second transistor; and a fourth transistor having a first terminal connected to the first terminal of the second transistor, a second terminal connected to the power source, and a control terminal connected to the first terminal of the first transistor.

A system includes a ring oscillator including an odd number of inverters arranged in a ring. The system also includes a time to digital converter including an odd number of flops, where each of the flops is coupled to an output of a different inverter. The system includes a level shifter coupled to the inverters and to the flops. The system also includes a Gray counter coupled to at least one of the flops. The system includes a decoder coupled to the time to digital converter. The system also includes a phase frequency detector coupled to the decoder.

A semiconductor device includes: a pair of input terminals or receiving a first input signal and a second input signal each of which changes between potentials in a predetermined range via a pair of transmission paths which include a first transmission path and a second transmission path; a first reception circuit which compares in potential the first input signal with the second input signal, and generates a first output signal based on a comparison result therebetween; a second reception circuit which generates a second output signal based on a comparison result of comparing in potential at least one of the first input signal and the second input signal with a reference potential.

Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.

A key reuse circuit is provided, a key component is used to generate a DC voltage and a startup-trigger-signal according to a user input, the switch circuit generates a key trigger signal according to the DC voltage, the control circuit reverses a level of an enable-regulation-signal when a time duration of the key trigger signal is longer than or equal to a preset time duration, or determines a key value of the key component when the time duration of the key trigger signal is shorter than the preset time duration, the power on/off regulation circuit generates a voltage-conversion-enable-signal according to the startup-trigger-signal and an enable-regulation-signal having a first level, the buck circuit generates a first voltage according to the power voltage and the voltage-conversion-enable-signal and stops generating the first voltage when the voltage-conversion-enable-signal is terminated, so that reuse of a general key in the key matrix is realized.

In an optocoupler circuit, a first direction path, which transmits signals from a first to a second terminal, includes a first level shifter, a second level shifter, and a first optocoupler. The first level shifter receives a first input signal at the first terminal, and shifts a voltage level of the first input signal to a first shifted voltage level with respect to a first ground level in a first power domain, to provide a first shifted signal. The first optocoupler receives the first shifted signal, and generates a first optocoupler signal in response to the first shifted signal. The second level shifter receives the first optocoupler signal, and shifts a voltage level of the first optocoupler signal to a second shifted voltage level with respect to a second ground level in a second power domain, to provide a second shifted signal at the second terminal.