An object is to improve Power Supply Rejection Ratio in a PLL circuit. A proportional path 103 is provided in a first power supply system 101 and outputs analog proportional signal AP according to a detection signal DET. An integral path 104 is provided in a second power supply system and outputs an analog integral signal AI according to the DET. A CCO driver 16 is provided in the first power supply system 101 and outputs control current ICCO according to the AP and the AI. A CCO 17 is provided in the second power supply system 102 and outputs an output signal Fout according to the ICCO. A phase frequency detector 11 is provided in the second power supply system 102 and configured to detect a phase difference between a reference signal Fref and a signal FM obtained by feeding back the Fout and then outputs the DET.

An output circuit has: a first driver circuit configured to receive a voltage of an input terminal and output a first voltage to an output terminal; a first comparison circuit configured to compare a first reference voltage with a voltage of the output terminal; a second driver circuit configured to receive the voltage of the input terminal and output a second voltage to the output terminal and become an off state according to a comparison result of the first comparison circuit; a second comparison circuit configured to compare a second reference voltage different from the first reference voltage with the voltage of the output terminal; and a third driver circuit configured to receive the voltage of the input terminal and output a third voltage to the output terminal and become an off state according to a comparison result of the second comparison circuit.

An oscillator circuit with an oscillator stage and a first current source arranged to drive the oscillator stage is presented. The oscillator stage has an oscillator stage input terminal, an oscillator stage output terminal, an oscillator arranged to provide an oscillating signal between the oscillator stage input terminal and the oscillator stage output terminal. The oscillator circuit has an operational amplifier with an inverting input, a non-inverting input and an operational amplifier output. The oscillator stage input terminal and the oscillator stage output terminal are coupled to the inverting input and non-inverting input. The operational amplifier output is coupled to the oscillator stage input terminal such that the oscillator stage input terminal and the oscillator stage output terminal are controlled to have a same DC voltage level.

A display driver integrated circuit (IC) and a display system including the same are provided. The display driver IC includes: a charge pump including a first node and a second node; a flying capacitor connected between the first node and the second node; a voltage regulator; a first switch connected between an output terminal of the voltage regulator and one of the first node and the second node; and a second switch connected between a ground and the other of the first node and the second node.

Presented systems and methods facilitate efficient reset operation. In one embodiment, a system comprises a core domain portion an I/O domain portion and a core reset I/O by-pass component. The core domain portion is configured to operate at a nominal core domain voltage level. The I/O domain portion configured to operate at a nominal I/O domain voltage level. The core reset I/O by-pass component configured to forward a reset indication to the core domain independent of the I/O domain. In one exemplary implementation the core reset I/O by-pass component is operable to receive an input reset indication at a high domain voltage level and to convert the input reset indication to a core reset signal that is less than or substantially equal to the nominal core domain voltage, wherein the high domain is voltage higher than the core domain voltage level.

A selection circuit, a method for controlling the selection circuit, and a multiplexing circuit are provided. The selection circuit includes N control circuits and M booster circuits. Control terminals of M control circuits among the N control circuits are coupled to output terminals of the M booster circuits, respectively, and first input terminals of the M booster circuits are coupled to receive M control signals among N control signals, respectively. Second input terminals of the M booster circuits are coupled to receive M boost signals respectively, and each booster circuit is configured to provide the received control signal to an output terminal of the booster circuit and increase a potential at the output terminal of the booster circuit by using the received boost signal.

A primary circuit outputs, in response to an input signal, a first signal with a first reference potential. A level shift main circuit converts the reference potential of the first signal received from the primary circuit to a second reference potential to output a second signal with the second reference potential. A secondary circuit generates an output signal with the second reference potential using the second signal. At least one rectifying element circuit is provided between the primary circuit and the secondary circuit. At least one of the primary circuit and the secondary circuit includes at least one detection circuit detecting a change in a current flowing through the rectifying element circuit to determine whether a potential corresponding to the second reference potential is lower than or equal to a potential corresponding to the first reference potential.

A capacitively-driven tunable coupler includes a coupling capacitor connecting an open end of a quantum object (i.e., an end of the object that cannot have a DC path to a low-voltage rail, such as a ground node, without breaking the functionality of the object) to an RF SQUID having a Josephson element capable of providing variable inductance and therefore variable coupling to another quantum object.

A system may include a pre-charge stage and a voltage converter. The pre-charge stage may include a controller circuit configured to generate a control voltage and a current regulator electrically coupled to the controller circuit and configured to generate a first voltage, a second voltage, and a third voltage. The voltage converter may include a capacitor, a hold capacitor, and switches. The capacitor may include a first plate and a voltage on the first plate may be equal to the first voltage. The capacitor may include a second plate and a voltage on the second plate may be equal to the second voltage. The hold capacitor may include a plate and a voltage on the plate may be equal to the third voltage. The current regulator may be configured to regulate a current on the switches during accumulation of an initial charge on the capacitor and the hold capacitor.

A transmitter circuit including a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit, and a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit may be provided.