The invention provides an apparatus comprising a programmable circuit including a plurality of 2-input 1-output ALUs, and an updating unit updating the programmable circuit according to circuit information, wherein each of the ALUs includes a calculation unit which performs a set type of calculation for two data and output a calculation result, a delay unit which delays the two input data in accordance with delay amounts independently set and supplies the delayed data to the calculation unit, and a controller which controls a delay amount for the delay unit and a calculation timing for the calculation unit in accordance with externally set information, wherein the updating unit sets clock gating start timings for a plurality of delay elements of the delay unit if an ALU of interest as a first processing circuit in the programmable circuit inputs final data to be processed.

An electronic device includes a die stack having a plurality of die. The die stack includes a die parity path spanning the plurality of die and configured to alternatingly identify each die as a first type or a second type. The die stack further includes an inter-die signal path spanning the plurality of die and configured to propagate an inter-die signal through the plurality of die, wherein the inter-die signal path is configured to invert a logic state of the inter-die signal between each die. Each die of the plurality of die includes signal formatting logic configured to selectively invert a logic state of the inter-die signal before providing it to other circuitry of the die responsive to whether the die is designated as the first type or the second type.

A digital signal processing block has a first input port, a second input port, a third input port, a cascade input port and an output port. The DSP block may have a cascade output port. The DSP block may have a multiplexer that has selectable output, to the cascade output port, of concatenated inputs from the first input port, the second input port and the third input port. The DSP block may be connectable to another DSP block via a cascade path. The DSP block may have a variable shifter. The DSP block may have a full-width adder and reduced-width input ports.

An analog circuit has a first plurality of transistors that are connected as a first selectable resistance in the analog circuit, and a second plurality of transistors that are connected as a second selectable resistance in the analog circuit. In an unlocked state of the analog circuit, the first selectable resistance matches the second selectable resistance within a designed ratio and tolerance. In a locked state of the analog circuit, the first selectable resistance and the second selectable resistance do not match within the designed ratio and tolerance. A controller retrieves a logic lock key from an off-chip memory and selects the first and second selectable resistances, thereby setting the analog circuit to its unlocked state, by sending respective first and second portions of the logic lock key to operate the first and second pluralities of transistors.

Technologies for providing efficient reprovisioning in an accelerator device include an accelerator sled. The accelerator sled includes a memory and an accelerator device coupled to the memory. The accelerator device is to configure itself with a first bit stream to establish a first kernel, execute the first kernel to produce output data, write the output data to the memory, configure itself with a second bit stream to establish a second kernel, and execute the second kernel with the output data in the memory used as input data to the second kernel. Other embodiments are also described and claimed.

A dynamic bias analog vector-matrix multiplication operation circuit and an operation control method therefor. The dynamic bias analog vector-matrix multiplication operation circuit comprises: positive value weight columns (10.sub.1-10.sub.N), constant columns (20.sub.1-20.sub.M) and subtractors (30.sub.1-30.sub.N), wherein the number of the subtractors is equal to the number of the positive value weight columns, the subtractors are correspondingly connected to the positive value weight columns on a one-to-one basis, and the number of the constant columns is less than the number of the positive value weight columns; minuend input ends of the subtractors are correspondingly connected to output ends of the positive value weight columns, subtrahend input ends thereof are connected to output ends of the constant columns, and output ends thereof output operation results; and subtrahend input ends of a plurality of subtractors are connected to the same constant column. Before a weight is written in a programmable semiconductor device, a constant positive value is added to each element in a weight array to obtain a weight array to be configured, said weight array is written in a positive value weight column, and the constant positive value is written in a constant column. Therefore, a negative value weight column does not need to be set, such that the circuit structure can be simplified.

An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.

A configurable input/output device includes a plurality of input/output terminals, a routing module, and a first universal input/output channel. The input/output terminals are connected a plurality of field devices. The input/output terminals receive a plurality of input signals from the field devices, and output a plurality of output signals to the field devices. At least two of the input signals are different, at least two of the output signals are different, and at least two the field devices are different. The routing module is connected to the input/output terminals. The first universal input/output channel is connected to the routing module. The routing module controls connections between the first universal input/output channel and the input/output terminals. The routing module also controls the transceiving sequence for the input signals and the output signals.

A digital signal processing (DSP) block includes a Fast Fourier Transform (FFT) unit capable of performing an FFT operation. The FFT unit includes a first FFT engine capable of converting a signal between a time-domain and a frequency-domain and the first FFT engine is a fixed size FFT engine. The FFT unit also includes a second FFT engine communicatively coupled to the first FFT engine and the second FFT engine is a variable size FFT engine. The FFT unit also includes a scale/offset block communicatively coupled to the second FFT engine and the scale/offset block is capable of performing a multiplication operation, an addition operation, or a combination thereof on an output of the second FFT engine.

An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.