An integrated circuit includes a region of logic circuits, first and second selector circuits, a first interface circuit for exchanging information with a first type of device according to a first communication protocol, and a second interface circuit for exchanging information with a second type of device according to a second communication protocol. The first selector circuit is configurable to provide signals between the region of the logic circuits and a selected one of the first or second interface circuits. The second selector circuit is configurable to provide signals between the selected one of the first or second interface circuits and the first or second type of device.

In one example, an electronic system includes, a user interface comprising an input device, a first actuator and a second actuator, the first and second actuators dually actuated by the input device, and a controller, including a comparator, a programmable device, and executable instructions residing in non-transitory memory thereon to, receive first and second output signals from the first and second actuators, respectively, convert the first and second output signals to first and second real-time logic states at the comparator, input the first and second real-time logic states from the comparator to the programmable device, and determine a fault status of the first and second actuators based on the first and second logic states input to a state machine of the programmable device, wherein the first and second logic states input to the state machine include the real-time logic states and historical logic states stored at the controller.

Identification of the types of input and output cards of a PLC and proper connection of field devices to a PLC are achieved by connecting a self-learning discrete input circuit and/or a self-learning discrete output circuit between the PLC and the field device.

Technologies for providing efficient reprovisioning in an accelerator device include an accelerator sled. The accelerator sled includes a memory and an accelerator device coupled to the memory. The accelerator device is to configure itself with a first bit stream to establish a first kernel, execute the first kernel to produce output data, write the output data to the memory, configure itself with a second bit stream to establish a second kernel, and execute the second kernel with the output data in the memory used as input data to the second kernel. Other embodiments are also described and claimed.

A programmable input/output (I/O) circuit includes an output buffer coupled between an output signal and an I/O pad and an input comparator coupled between an input signal and the I/O pad. The input comparator includes a first input coupled to the I/O pad. A multiplexor receives a select signal for selecting a first reference voltage from the plurality of reference voltages at a first time and for dynamically selecting a second reference voltage from the plurality of reference voltages at a second time.

An electronic environmental sensor tag includes microsensor elements using magnetic logic devices adapted to detect target chemical and/or target environmental conditions. The microsensor elements operate only periodically to save power, and also include non-volatile memories and communications circuits to allow interrogation and detection of a target condition.

An integrated circuit to drive a plurality of fluid actuation devices includes a contact pad and a programmable pulldown device. The programmable pulldown device is electrically coupled to the contact pad. The programmable pulldown device is settable to any one of a plurality of resistances.

An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.

A fail-safe power limit (FSPL) can be applied to components that lose communication with a management module (MM) to determine a safe power level at which to operate. The FSPL may be computed by the management module (MM) for the information handling system and distributed to components in the information handling system. By computing a FSPL and transmitting the FSPL to the components, a larger amount of the available power can be used by the components. This allows the components to continue operating at performance levels closer to or equivalent to levels available when the management module (MM) is operating normally. The FSPL may be updated at set times and/or on a periodic schedule such that the FSPL used by the components when communication is lost with the management module (MM) reflects a recent operating state of the components.

Identification of the types of input and output cards of a PLC and proper connection of field devices to a PLC are achieved by connecting a self-learning discrete input circuit and/or a self-learning discrete output circuit between the PLC and the field device.