The disclosure describes various aspects of a practical implementation of multi-qubit gate architecture. A method is described that includes enabling ions in the ion trap having three energy levels, enabling a low-heating rate motional mode (e.g., zig-zag mode) at a ground state of motion with the ions in the ion trap; and performing a Cirac and Zoller (CZ) protocol using the low-heating rate motional mode as a motional state of the CZ protocol and one of the energy levels as an auxiliary state of the CZ protocol, where performing the CZ protocol includes implementing the multi-qubit gate. The method also includes performing one or more algorithms using the multi-qubit gate, including Grover's algorithm, Shor's factoring algorithm, quantum approximation optimization algorithm (QAOA), error correction algorithms, and quantum and Hamiltonian simulations. A corresponding system that supports the implementation of a multi-qubit gate architecture is also described.

Examples are disclosed that relate to dynamically controlling light sources on an optically trackable peripheral device. One disclosed example provides a near-eye display device comprising an image sensor, a communications subsystem, a logic subsystem, and a storage subsystem. The storage subsystem stores instructions executable by the logic subsystem to control a peripheral device comprising a plurality of light sources by receiving image data from the image sensor, identifying in the image data a constellation of light sources formed by a subset of light sources of the peripheral device, and based upon the constellation of light sources identified, send to the peripheral device via the communications subsystem constellation information related to the constellation of light sources identified.

Examples are disclosed that relate to dynamically controlling light sources on an optically trackable peripheral device. One disclosed example provides a near-eye display device comprising an image sensor, a communications subsystem, a logic subsystem, and a storage subsystem. The storage subsystem stores instructions executable by the logic subsystem to control a peripheral device comprising a plurality of light sources by receiving image data from the image sensor, identifying in the image data a constellation of light sources formed by a subset of light sources of the peripheral device, and based upon the constellation of light sources identified, send to the peripheral device via the communications subsystem constellation information related to the constellation of light sources identified.

A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.

A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.

The method object of the invention enables the scalable configuration and performance optimisation to be carried out for programmable optical circuits based on meshed structures, in such a way that they can perform optical/quantum signal processing functions. The object of the invention can be applied in circuits with arbitrary degrees of complexity implemented by means of programming a waveguide mesh. The method object of the invention enables not only the analysis and evaluation of performance to be carried out, but also the subsequent programming and optimisation of programmable optical devices.

The disclosure describes various aspects of a practical implementation of multi-qubit gate architecture. A method is described that includes enabling ions in the ion trap having three energy levels, enabling a low-heating rate motional mode (e.g., zig-zag mode) at a ground state of motion with the ions in the ion trap; and performing a Cirac and Zoller (CZ) protocol using the low-heating rate motional mode as a motional state of the CZ protocol and one of the energy levels as an auxiliary state of the CZ protocol, where performing the CZ protocol includes implementing the multi-qubit gate. The method also includes performing one or more algorithms using the multi-qubit gate, including Grover's algorithm, Shor's factoring algorithm, quantum approximation optimization algorithm (QAOA), error correction algorithms, and quantum and Hamiltonian simulations. A corresponding system that supports the implementation of a multi-qubit gate architecture is also described.

The disclosure describes various aspects of a practical implementation of multi-qubit gate architecture. A method is described that includes enabling ions in the ion trap having three energy levels, enabling a low-heating rate motional mode (e.g., zig-zag mode) at a ground state of motion with the ions in the ion trap; and performing a Cirac and Zoller (CZ) protocol using the low-heating rate motional mode as a motional state of the CZ protocol and one of the energy levels as an auxiliary state of the CZ protocol, where performing the CZ protocol includes implementing the multi-qubit gate. The method also includes performing one or more algorithms using the multi-qubit gate, including Grover's algorithm, Shor's factoring algorithm, quantum approximation optimization algorithm (QAOA), error correction algorithms, and quantum and Hamiltonian simulations. A corresponding system that supports the implementation of a multi-qubit gate architecture is also described.

An image sensing device capable of minimizing reflection of light incident upon a metal layer is disclosed. The image sensing device includes a semiconductor substrate in which at least one groove is formed, a reflection prevention layer formed over the semiconductor substrate in a manner that the at least one groove is buried by the reflection prevention layer, and a metal layer formed over the reflection prevention layer, and provided with at least one through-hole corresponding to the at least one groove.

A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.