Disclosed is a magnetic logic device including: a plurality of input branches configured by a magnetic nanowire including a non-magnetic metallic layer, a free layer, and an insulating layer sequentially stacked; an output branch configured by the magnetic nanowire; a coupling portion configured by the magnetic nanowire and where the input branches and the output branch meet; gate electrodes arranged adjacent to the insulating layer in each of the plurality of input branches; and in-plane anisotropic ferromagnetic layers arranged adjacent to the non-magnetic metallic layer in each of the plurality of input branches.

Logic circuits constructed with magnetoelectric (ME) transistors are described herein. A ME logic gate device can include at least one conducting device, for example, at least one MOS transistor; and at least one ME transistor coupled to the at least one conducting device. The ME transistor can be a ME field effect transistor (ME-FET), which can be can be an anti-ferromagnetic spin-orbit read (AFSOR) device or a non-AFSOR device. The gates and logic circuits described herein can be included as standard cells in a design library. Cells of the cell library can include standard cells for a ME inverter device, a ME minority gate device, a ME majority gate device, a ME full adder, a ME XNOR device, a ME XOR device, or a combination thereof.

Logic circuits constructed with magnetoelectric (ME) transistors are described herein. A ME logic gate device can include at least one conducting device, for example, at least one MOS transistor; and at least one ME transistor coupled to the at least one conducting device. The ME transistor can be a ME field effect transistor (ME-FET), which can be can be an anti-ferromagnetic spin-orbit read (AFSOR) device or a non-AFSOR device. The gates and logic circuits described herein can be included as standard cells in a design library. Cells of the cell library can include standard cells for a ME inverter device, a ME minority gate device, a ME majority gate device, a ME full adder, a ME XNOR device, a ME XOR device, or a combination thereof.

A computing device including a logic track including two logic-track magnetic domains separated by a logic-track domain wall, an input track arranged crossing the logic track at a first position of the logic track, and an output track arranged crossing the logic track at a second position of the logic track near the logic-track domain wall. The input track includes at least one input-track magnetic domain, and each of the at least one input-track magnetic domain includes at least one input-track storage unit configured to store binary 0 or 1. The output track includes at least one output-track magnetic domain, and each of the at least one output-track magnetic domain includes at least one output-track storage unit configured to store binary 0 or 1.

A computing device including a logic track including two logic-track magnetic domains separated by a logic-track domain wall, an input track arranged crossing the logic track at a first position of the logic track, and an output track arranged crossing the logic track at a second position of the logic track near the logic-track domain wall. The input track includes at least one input-track magnetic domain, and each of the at least one input-track magnetic domain includes at least one input-track storage unit configured to store binary 0 or 1. The output track includes at least one output-track magnetic domain, and each of the at least one output-track magnetic domain includes at least one output-track storage unit configured to store binary 0 or 1.

Disclosed is a magnetic logic device including: a plurality of input branches configured by a magnetic nanowire including a non-magnetic metallic layer, a free layer, and an insulating layer sequentially stacked; an output branch configured by the magnetic nanowire; a coupling portion configured by the magnetic nanowire and where the input branches and the output branch meet; gate electrodes arranged adjacent to the insulating layer in each of the plurality of input branches; and in-plane anisotropic ferromagnetic layers arranged adjacent to the non-magnetic metallic layer in each of the plurality of input branches.

Disclosed is a magnetic logic device including: a plurality of input branches configured by a magnetic nanowire including a non-magnetic metallic layer, a free layer, and an insulating layer sequentially stacked; an output branch configured by the magnetic nanowire; a coupling portion configured by the magnetic nanowire and where the input branches and the output branch meet; gate electrodes arranged adjacent to the insulating layer in each of the plurality of input branches; and in-plane anisotropic ferromagnetic layers arranged adjacent to the non-magnetic metallic layer in each of the plurality of input branches.

A magneto-electric (ME) majority gate device includes a conducting device and a plurality of ME transistors coupled to the conducting device. In one implementation, the plurality of ME transistors include a ME AND gate device with downward interface polarization, a ME-transmission gate device with downward interface polarization, and a ME-XNOR gate device. In another implementation, the plurality of ME transistors is five single-input ME-FETs.

A magneto-electric (ME) majority gate device includes a conducting device and a plurality of ME transistors coupled to the conducting device. In one implementation, the plurality of ME transistors include a ME AND gate device with downward interface polarization, a ME-transmission gate device with downward interface polarization, and a ME-XNOR gate device. In another implementation, the plurality of ME transistors is five single-input ME-FETs.

A magneto-electric (ME) XNOR logic gate device includes a conducting device; and a ME-FET coupled to the conducting device. The ME-FET can be formed of a split gate; a first gate terminal coupled to a first portion of the split gate for receiving a first input signal; a second gate terminal coupled to a second portion of the split gate for receiving a second input signal; a source terminal coupled to a ground line; and a drain terminal coupled to the conducting device.