Logic circuits constructed with magnetoelectric (ME) transistors are described herein. A ME logic gate device can include at least one conducting device, for example, at least one MOS transistor; and at least one ME transistor coupled to the at least one conducting device. The ME transistor can be a ME field effect transistor (ME-FET), which can be can be an anti-ferromagnetic spin-orbit read (AFSOR) device or a non-AFSOR device. The gates and logic circuits described herein can be included as standard cells in a design library. Cells of the cell library can include standard cells for a ME inverter device, a ME minority gate device, a ME majority gate device, a ME full adder, a ME XNOR device, a ME XOR device, or a combination thereof.

Logic circuits constructed with magnetoelectric (ME) transistors are described herein. A ME logic gate device can include at least one conducting device, for example, at least one MOS transistor; and at least one ME transistor coupled to the at least one conducting device. The ME transistor can be a ME field effect transistor (ME-FET), which can be can be an anti-ferromagnetic spin-orbit read (AFSOR) device or a non-AFSOR device. The gates and logic circuits described herein can be included as standard cells in a design library. Cells of the cell library can include standard cells for a ME inverter device, a ME minority gate device, a ME majority gate device, a ME full adder, a ME XNOR device, a ME XOR device, or a combination thereof.

An anti-ferromagnetic (AFM) voltage-controlled field effect logic device structure can include an AFM material that extends in a first direction and an input voltage terminal that extends opposite the AFM material. An oxide material can be located between the AFM material and the input voltage terminal. A first spin orbital coupling (SOC) material can extend in a second direction across the AFM material to provide a first SOC channel with a drain voltage terminal at a first end of the first SOC channel and an output voltage terminal at a second end of the first SOC channel that is opposite the first end. A contact can be electrically coupled to the output voltage terminal and configured to electrically couple to a second SOC material extending in the second direction spaced apart from the first SOC material to provide a second SOC channel.

An anti-ferromagnetic (AFM) voltage-controlled field effect logic device structure can include an AFM material that extends in a first direction and an input voltage terminal that extends opposite the AFM material. An oxide material can be located between the AFM material and the input voltage terminal. A first spin orbital coupling (SOC) material can extend in a second direction across the AFM material to provide a first SOC channel with a drain voltage terminal at a first end of the first SOC channel and an output voltage terminal at a second end of the first SOC channel that is opposite the first end. A contact can be electrically coupled to the output voltage terminal and configured to electrically couple to a second SOC material extending in the second direction spaced apart from the first SOC material to provide a second SOC channel.

A spin wave control device includes a first magnetic layer, a second magnetic layer arranged above the first magnetic layer, and a capping layer overlapping a portion of the second magnetic layer. The first magnetic layer has a magnetization pointing in a first direction and the second magnetic layer has a magnetization pointing in a second direction that is approximately opposite to the first direction. The capping layer has a magnetization pointing approximately in the first direction or approximately in the second direction.

Methods and apparatus for complex number generation and operation on a chip are disclosed. A disclosed logic device includes a first magnet with a first preferred direction of magnetization to polarize a spin of electrons in the first direction. The example logic device includes a second magnet with a second preferred direction of magnetization that polarizes a spin of electrons in the second direction. The example logic device includes a third magnet providing a free layer without a preferred direction of magnetization that is connected to the first and second magnets, wherein the third magnet encodes a vector based on a flux of electrons spin polarized in the first direction and a flux of electrons spin polarized in the second direction.

Methods and apparatus for complex number generation and operation on a chip are disclosed. A disclosed logic device includes a first magnet with a first preferred direction of magnetization to polarize a spin of electrons in the first direction. The example logic device includes a second magnet with a second preferred direction of magnetization that polarizes a spin of electrons in the second direction. The example logic device includes a third magnet providing a free layer without a preferred direction of magnetization that is connected to the first and second magnets, wherein the third magnet encodes a vector based on a flux of electrons spin polarized in the first direction and a flux of electrons spin polarized in the second direction.

Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a corresponding spin current; and a stack of metal layers configured to convert the corresponding spin current to a second charge current, wherein the stack of metal layers is coupled to the input magnet.

Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a corresponding spin current; and a stack of metal layers configured to convert the corresponding spin current to a second charge current, wherein the stack of metal layers is coupled to the input magnet.

The present disclosure relates to a structure including a memory array circuit with a magnetic tunnel junction array and an inverter between at least two data magnetic tunnel junctions and configured to enable logic-in-memory computations.