An integrated circuit includes first and second circuit blocks. The first circuit block includes a first storage circuit. A first data path passes through the first storage circuit and a first multiplexer circuit to a first input of a first logic circuit. The first multiplexer circuit is coupled to the first storage circuit. A second storage circuit is coupled between the first storage circuit and the first multiplexer circuit. A second data path passes through the second circuit block to a second input of the first logic circuit. The first multiplexer circuit is configurable to bypass or to couple the second storage circuit in the first data path based on an indication of whether a redundant third circuit block is coupled between the first and second circuit blocks in at least one of the first data path or the second data path.

Systems and methods for time-multiplexed synchronous logic provide an enhanced time delay multiplexing (TDM) scheme that includes soft TDM logic generated by computer-aided design (CAD) tools to actualize a circuit design with improved density. The CAD tools can be used to utilize inherent regularity to devise time multiplexing user logic. The CAD can generate soft TDM hardware to realize a circuit design with improved density.

A transmitter circuit including a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first voltage, the pre-driver circuit including a transistor having a threshold voltage equal to or lower than a threshold voltage of a transistor included in the logic circuit, and a main-driver circuit configured to receive the first signal and generate a second signal driven by a second voltage, the main-driver circuit configured to output the second signal to an input/output pad, the main-driver circuit including a transistor having a threshold voltage which is equal to or lower than the threshold voltage of the transistor included in the logic circuit may be provided.

Systems and techniques for configuration of a system on a programmable chip (SOPC) are described. By configuring the SOPC, during power-up, with a voltage input instead of with a flash memory or another non-volatile memory, the systems and techniques may save cost and board space.

A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.

An arithmetic logic operation device including a memory device configured to store a lookup table and receive an input of a bit string N bits long, N being an integer of at least 2, the input bit string representing an address in the lookup table at which is stored multiple-bit data of which a part includes a bit representative of the result of a logical operation performed between the bits included in the input bit string. The memory device is accessed to output the bits included in the data stored at the address represented by the received bit string. The arithmetic logic device achieves arithmetic processing in a relatively short time on a relatively small circuit scale.

The disclosure relates to technology for configuring programmable logic devices having multiple programmable hardware units configurable in one or more functional modes. The programmable hardware units are coupled to independent switch devices (e.g., multiplexers) that select configuration patterns stored in a common and shared configuration memory. The configuration memory includes a set of configuration registers to store the configuration patterns, which configuration patterns correspond to the one or more functional modes. The configuration registers may be addressed using an index of addresses stored in memory that identify a select line in one of the switch devices for a particular programmable hardware unit. Each select line in a switch device corresponds to a particular one of the configuration registers storing the configuration pattern. The addressed configuration register is accessed to retrieve the configuration pattern and configure the programmable hardware unit.

A resonance frequency is adjusted or optimized by shifting the resonance frequency without reducing an impedance function or a withstand voltage characteristic against a high frequency noise, when blocking, by using a multiple parallel resonance characteristic of a distributed constant line, the high frequency noise introduced into a line such as a power feed line or a signal line from an electrical member other than a high frequency electrode within a processing vessel. Regarding winding pitches, each of the solenoid coils 104(1) and 104(2) is divided to multiple sections K.sub.1, K.sub.2, . . . in a coil axis direction, and, a winding pitch p.sub.i in each section K.sub.i (i=1, 2, . . . ) is set independently. Comb teeth M inserted into winding gaps of both solenoid coils 104(1) and 104(2) are formed on inner surfaces of multiple rod-shaped comb-teeth member 114 provided adjacent to the solenoid coils 104(1) and 104(2).

A method for upgrading a programmable logic device (PLD) in a network element is provided. The method includes writing PLD configuration data to a nonvolatile memory and directing a signal control device external to the PLD to hold system control signals in the network element at a predefined state irrespective of direction by the PLD. The method includes loading the PLD configuration data from the nonvolatile memory into a PLD configuration memory in the PLD, while the signal control device holds the system control signals at the predefined values. The method includes directing the signal control device to release the holding the system control signals, so that the PLD directs the system control signals, responsive to completion of the loading the PLD configuration data into the PLD configuration memory. A network element is also provided.

A method for upgrading a programmable logic device (PLD) in a network element is provided. The method includes writing PLD configuration data to a nonvolatile memory and directing a signal control device external to the PLD to hold system control signals in the network element at a predefined state irrespective of direction by the PLD. The method includes loading the PLD configuration data from the nonvolatile memory into a PLD configuration memory in the PLD, while the signal control device holds the system control signals at the predefined values. The method includes directing the signal control device to release the holding the system control signals, so that the PLD directs the system control signals, responsive to completion of the loading the PLD configuration data into the PLD configuration memory. A network element is also provided.