A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y≠q, where q is a pre-determined value (e.g., such as 0 or 1).

A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y≠q, where q is a pre-determined value (e.g., such as 0 or 1).

A hybrid quantum-classical (HQC) computing system, including a quantum computing component and a classical computing component, computes the inverse of a Boolean function for a given output. The HQC computing system translates a set of constraints into interactions between quantum spins; forms, from the interactions, an Ising Hamiltonian whose ground state encodes a set of states of a specific input value that are consistent with the set of constraints; performs, on the quantum computing component, a quantum optimization algorithm to generate an approximation to the ground state of the Ising Hamiltonian; and measures the approximation to the ground state of the Ising Hamiltonian, on the quantum computing component, to obtain a plurality of input bits which are a satisfying assignment of the set of constraints.

A hybrid quantum-classical (HQC) computing system, including a quantum computing component and a classical computing component, computes the inverse of a Boolean function for a given output. The HQC computing system translates a set of constraints into interactions between quantum spins; forms, from the interactions, an Ising Hamiltonian whose ground state encodes a set of states of a specific input value that are consistent with the set of constraints; performs, on the quantum computing component, a quantum optimization algorithm to generate an approximation to the ground state of the Ising Hamiltonian; and measures the approximation to the ground state of the Ising Hamiltonian, on the quantum computing component, to obtain a plurality of input bits which are a satisfying assignment of the set of constraints.

An example apparatus comprises an array of memory cells coupled to sensing circuitry including a first sense amplifier, a second sense amplifier, and a logical operation component. The sensing circuitry may be controlled to sense, via first sense amplifier, a data value stored in a first memory cell of the array, sense, via a second sense amplifier, a data value stored in a second memory cell of the array, and operate the logical operation component to output a logical operation result based on the data value stored in the first sense amplifier and the data value stored in the second sense amplifier.

A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

A processing system includes a pseudo-random bit sequence (PRBS) control unit and a PRBS generator that is used to dynamically generate a PRBS from, for example, a first PRBS and a second PRBS. The PRBS generator is coupled to the PRBS control unit. The PRBS generator generates the second PRBS by dynamically adjusting from a first set of flip-flops of a master set of flip-flops that generate the first PRBS to a second set of flip-flops of the first master set of flip-flops that generate the second PRBS. The PRBS generator includes a plurality of PRBS logic engines coupled to a first PRBS multiplexer, the first PRBS multiplexer being used to select either the first PRBS or the second PRBS that is output by the PRBS generator.

A processing system includes a pseudo-random bit sequence (PRBS) control unit and a PRBS generator that is used to dynamically generate a PRBS from, for example, a first PRBS and a second PRBS. The PRBS generator is coupled to the PRBS control unit. The PRBS generator generates the second PRBS by dynamically adjusting from a first set of flip-flops of a master set of flip-flops that generate the first PRBS to a second set of flip-flops of the first master set of flip-flops that generate the second PRBS. The PRBS generator includes a plurality of PRBS logic engines coupled to a first PRBS multiplexer, the first PRBS multiplexer being used to select either the first PRBS or the second PRBS that is output by the PRBS generator.

According to one embodiment, a bus buffer circuit includes an input buffer circuit that receives an input signal, and outputs a non-inversion input signal and an inversion input signal, a voltage conversion circuit that operates by a second power supply, performs voltage conversion on the non-inversion input signal and the inversion input signal input thereto, and outputs the signals as a voltage-converted non-inversion output signal and a voltage-converted inversion output signal, an output retaining circuit that retains the voltage-converted non-inversion output signal and the voltage-converted inversion output signal at a same potential level when an output enable signal is in a disable state, a determinator that determines whether these signals are at a same potential level, a three-state output buffer circuit that outputs the voltage-converted non-inversion output signal or the voltage-converted inversion output signal from an output terminal, and an output controller that sets the three-state output buffer circuit in an output disable state, when the voltage-converted non-inversion output signal and the voltage-converted inversion output signal are at a same potential level, on a basis of an outcome of the determinator. Therefore, it is possible to prevent a potential different from the actual bus signal from being temporarily output during an output state transition, in a case where the state is fixed to reduce the power consumption.