A plurality voter circuit is disclosed. The plurality voter circuit includes an input array, an output, a control unit, a priority unit and a bypass unit. The output includes an element of the input array with the highest plurality in the input array, which is an output of the bypass unit. The input array is loaded into the control unit and the bypass unit. In addition, the control unit, the priority unit and the bypass unit are electrically connected.

A plurality voter circuit is disclosed. The plurality voter circuit includes an input array, an output, a control unit, a priority unit and a bypass unit. The output includes an element of the input array with the highest plurality in the input array, which is an output of the bypass unit. The input array is loaded into the control unit and the bypass unit. In addition, the control unit, the priority unit and the bypass unit are electrically connected.

Described is an interconnect which comprises: a first end having a ferromagnetic layer coupled to a first magnetoelectric material layer; and a second end having a second magnetoelectric material layer coupled to the ferromagnetic layer, wherein the ferromagnetic layer extends from the first end to the second end. Described is a majority gate device which comprises: a ferromagnetic layer; and first, second, third, and fourth magnetoelectric material layers coupled to the ferromagnetic layer. Described is an apparatus which comprises: a first end having a ferromagnetic layer coupled to a first magnetoelectric material layer; and a second end having a tunnel junction device coupled to the ferromagnetic layer. Described is an apparatus which comprises: a first terminal coupled to a tunneling junction device; a second terminal coupled to a layer coupling the tunneling junction device and a magnetoelectric device; and a third terminal coupled to the magnetoelectric device.

This invention comprises an integrated circuit in CMOS technology which can act as a regular sequential logic latch, having one data signal input, or as a voting latch, having three data signal inputs. The circuit schematic of this integrated circuit is such that it allows for a certain placement of the devices in the physical, manufactured integrated circuit that makes it possible to optimize the arrangement of the n-type MOSFET devices and p-type MOSFET devices in the circuit independently, using the Layout Optimization through Error Aware Positioning (LEAP), and thereby to remove, or reduce, the occurrence of radiation generated soft errors.

This invention comprises an integrated circuit in CMOS technology which can act as a regular sequential logic latch, having one data signal input, or as a voting latch, having three data signal inputs. The circuit schematic of this integrated circuit is such that it allows for a certain placement of the devices in the physical, manufactured integrated circuit that makes it possible to optimize the arrangement of the n-type MOSFET devices and p-type MOSFET devices in the circuit independently, using the Layout Optimization through Error Aware Positioning (LEAP), and thereby to remove, or reduce, the occurrence of radiation generated soft errors.

This patent document provides implementations and examples of circuits and devices based on low-energy consumption semiconductor structures exhibiting multi-valued states. In one aspect, a semiconductor device is configured to comprise: a multi-layer structure forming a magnetoelectric or multiferroic system to include a ferromagnetic, magnetostrictive layer that exhibits a biaxial magnetic anisotropy and an underlying metal structure exhibits a spin Hall effect to provide a conversion between electrical energy and magnetic energy with more than two distinctive magnetic states.

A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.

Integrated circuits such as application specific integrated circuits or programmable logic devices may include multiple copies of a same circuit together with a majority vote circuit in a configuration that is sometimes also referred to as multi-mode redundancy. An adder circuit may be coupled to these multiple copies and produce a carry-out signal and a sum signal based on signals received from the multiple copies. The carry-out signal of the adder circuit may provide the result of the majority vote operation. A logic exclusive OR gate may perform a logic exclusive OR operation between the sum signal and the carry-out signal, thereby generating an error signal. The error signal may indicate that one of the multiple copies produces an output that is different than the outputs produced by the other copies.

Integrated circuits such as application specific integrated circuits or programmable logic devices may include multiple copies of a same circuit together with a majority vote circuit in a configuration that is sometimes also referred to as multi-mode redundancy. An adder circuit may be coupled to these multiple copies and produce a carry-out signal and a sum signal based on signals received from the multiple copies. The carry-out signal of the adder circuit may provide the result of the majority vote operation. A logic exclusive OR gate may perform a logic exclusive OR operation between the sum signal and the carry-out signal, thereby generating an error signal. The error signal may indicate that one of the multiple copies produces an output that is different than the outputs produced by the other copies.

The disclosed technology generally relates to magnetic devices and more particularly to spin torque majority gate devices, and to methods of operating such devices. In one aspect, a majority gate device comprises a free ferromagnetic layer comprising 3N input zones and an output zone. The output zone has a polygon shape having 3N sides, where each input zone adjoins the output zone. The input zones are arranged around the output zone according to a 3N-fold rotational symmetry, where N is a positive integer greater than 0. The input zones are spaced apart from one another by the output zone. The majority gate device additionally comprises a plurality of input controls, where each of the input zones is magnetically coupled to a corresponding one of the plurality of input controls, where each of the input controls is configured to control the magnetization state of the corresponding input zone. The majority gate device further comprises an output sensor magnetically coupled to the output zone, where the output sensor is adapted for sensing the magnetization state of the output zone. Each input zones adjoins the output zone at one of the 3N sides.