At least one embodiment of the present disclosure provides a frequency divider, an electronic device and a frequency dividing method. The frequency divider includes a duty cycle correction circuit and a frequency divider circuit. The duty cycle correction circuit is configured to receive a first clock signal, and perform a first processing on the first clock signal to generate a first processed signal. The frequency dividing circuit is configured to receive the first processed signal, and perform a second processing on the first processed signal to generate a second processed signal. The duty cycle correction circuit is further configured to receive the second processed signal, and perform a third processing on the second processed signal to generate a third processed signal. The frequency divider can correct the duty cycle of the output clock signal while dividing the frequency.

An integrated circuit device for reservoir computing can include a weighted input layer, an unweighted, asynchronous, internal recurrent neural network made up of nodes having binary weighting, and a weighted output layer. Weighting of output signals can be performed using predetermined weighted sums stored in memory. Application specific integrated circuit (ASIC) embodiments may include programmable nodes. Characteristics of the reservoir of the device can be tunable to perform rapid processing and pattern recognition of signals at relatively large rates.

Embodiments relate to a clock counter, a method for clock counting, and a storage apparatus. The clock counter includes a clock frequency-dividing circuit, a plurality of counting circuits, and an adding circuit. The clock frequency-dividing circuit receives a clock signal and divide a frequency of the clock signal to output a plurality of frequency-divided clock signals, sum of number of pulses of the plurality of frequency-divided clock signals being equal to number of pulses of the clock signal. The plurality of counting circuits are connected to the clock frequency-dividing circuit, each of the plurality of counting circuits being configured to respectively count pulses for each of the plurality of frequency-divided clock signals and generate an initial count value. The adding circuit is connected to the plurality of counting circuits, and adds up the initial count values of the plurality of counting circuits to generate a target count value.

Disclosed are a circuit unit, a circuit module and an apparatus for data statistics. The circuit unit comprises a first register and a second register, and stores data received via a first input terminal in the first register in a case where a first control terminal receives a valid control signal, stores data received via a second input terminal in the second register in a case where a second control terminal receives a valid control signal, and increases the value of data stored in the second register by 1 in a case where a third control terminal receives a valid control signal. The circuit module comprises one or more such circuit units, and the apparatus comprises one or more such circuit modules. The circuit module or the apparatus may use smaller resource and smaller power consumption to complete data statistics.

Disclosed are a circuit unit, a circuit module and an apparatus for data statistics. The circuit unit comprises a first register and a second register, and stores data received via a first input terminal in the first register in a case where a first control terminal receives a valid control signal, stores data received via a second input terminal in the second register in a case where a second control terminal receives a valid control signal, and increases the value of data stored in the second register by 1 in a case where a third control terminal receives a valid control signal. The circuit module comprises one or more such circuit units, and the apparatus comprises one or more such circuit modules. The circuit module or the apparatus may use smaller resource and smaller power consumption to complete data statistics.

The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.

The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values. The control signal generator is configured to generate a control signal based on an input clock signal and values in the at least a portion of the registers, wherein the control generator sequentially generates the control signal during each cycle of the input clock signal. The clock gating circuit is configured to refer to the control signal to mask or not mask the input clock signal to generate an output clock signal.

Counter, pixel circuit, display panel, display device are provided. The counter includes: start-up circuit generating and outputting start-up signal by clock signal; M first and M second combinational logic circuits, alternate and cascaded, where M is integer no less than 1. Input terminal of first combinational logic circuit is coupled to output terminal of start-up circuit or second combinational logic circuit of previous stage, input terminal of second combinational logic circuit is coupled to output terminal of first combinational logic circuit of previous stage. Clock signal terminals of first, second combinational logic circuits are for inputting clock signal. First combinational logic circuit is for outputting clock signal in first time period and continuously outputting low level signal in second time period. Second combinational logic circuit is for outputting inverted signal of clock signal in third time period and continuously outputting low level signal in fourth time period.

First and second pulse height detection circuits output pulse height detection signals which rise when a detection pulse obtained from a radiation detector becomes greater than a lower threshold Lsh or an upper threshold Hsh, and fall when the detection pulse is smaller than the lower threshold Lsh or the upper threshold Hsh. Next, first and second rising and falling detection circuits detect rising and falling edges of the pulse height detection signals from the first and second pulse height detection circuits in synchronization with a clock pulse from a crystal oscillator, and a combining circuit outputs a signal corresponding to the detection pulse that is within a range between the lower threshold Lsh and the upper threshold Hsh by combining both outputs from the first and second rising and falling detection circuits, in synchronization with the clock pulse.