A semiconductor apparatus may be provided. The semiconductor apparatus may include a first buffer configured to generate a first preliminary clock and a first preliminary clock bar based on an external clock, an external clock bar, and a node voltage code. The semiconductor apparatus may include a node voltage control circuit configured to generate the node voltage code based on a control code.

A semiconductor device includes a first oscillator circuit, a clock monitoring circuit and a timing signal generation circuit for periodically switching the operating mode of the clock monitoring circuit to one of the first to third modes. The clock monitoring circuit includes: a clock counter configured for counting the number of oscillations of the clock signal in the first mode and configured for shifting the pulses of the input signal to the output signal at normal time in the third mode; a comparison circuit for comparing whether the count value per predetermined period by the clock counter is within an expected value in the second mode; and an edge detection circuit for detecting whether the pulses of the input signal are shifted to the output signal of the clock counter in the third mode.

Within the integrated circuit there are a significant number of components and not all of them are electronic switches. In an effort to increase data speeds, lower power consumption, simplify circuits increase functionality within the integrated circuit, and increase the overall processing power of the circuit chip the use fiber-optic transmission lines as a communication medium between logic circuits instead of metallic conductors is more effective when utilized within the circuit chip. This would be used purely for the transmission of data and communication. With fiber-optic transmission lines, microscopic LED's and photodiode's the electronic/electrical design of logic gates would become simpler, there would be faster communication, less corrupted data, and a longer lifespan for the semiconductor circuit chips that are data processors.

Various embodiments relate to multi-modulus frequency dividers, devices including the same, and associated methods of operation. A method of operating a multi-modulus divider (MMD) may include determining a common state for the MMD, wherein the MMD is configured to enter the common state regardless of a divisor value applied to the MMD. The method may further include receiving an integer value at the MMD. Further, the method may include setting the divisor value equal to the integer value. The method may also include receiving an input signal at a first frequency and generating an output signal at a second, lower frequency based on the divisor value. The method may also include receiving a second integer value at the MMD. The method may further include setting the divisor value equal to the second integer value in response to a detected current state of the MMD matching the common state for the MMD.

A clock circuit includes a circuit configured to use a regulated voltage on a regulated voltage node to provide a frequency modulated clock signal having a frequency vacillating between a first frequency and a second frequency. The clock circuit includes an auxiliary loading circuit coupled to the regulated voltage node and configured to selectively provide load compensation for a load difference of the circuit. The load difference is a difference between a first load corresponding to the first frequency and a second load corresponding to the second frequency. The circuit may include a frequency divider circuit configured to use the regulated voltage on the regulated voltage node to generate the frequency modulated clock signal by frequency dividing an input clock signal according to a divide value vacillating between a first divide value and a second divide value.

A divider includes divider stages that may be turned off without toggling to extend the divide range of the divider while also reducing the impact of spurs on the divider output, and preserving the timing margin to update the divide ratio glitchlessly. A divider stage responds to an input enable signal being deasserted and a modulus input signal being asserted to remain in a disabled state in which the divider stage does not toggle by ensuring storage elements outputs in the divider stage remain constant. The divider further selects an update clock for the divide ratio of the divider utilizing an output from a most downstream stage that remains enabled.

A semiconductor device may include an input control circuit, a counting circuit, an output control circuit, and a counting operation control circuit. The input control circuit may output a counting input signal based on an input signal and a counting over signal. The counting circuit may generate a preliminary counting code based on the counting input signal. The output control circuit may generate a counting code based on the preliminary counting code. The counting operation control circuit may generate the counting over signal based on a part of the counting code.

A frequency divider includes a set of frequency-dividing units coupled in series in a sequential order, with the sequence of frequency-dividing units including a lowest unit and a highest unit, with the remaining units being disposed in series between the lowest unit and the highest unit. The lowest unit is coupled to receive an input clock whose frequency is to be divided and provided as an output clock. Each frequency-dividing unit in the set is coupled to receive a corresponding first clock as an input and is operable to generate a corresponding second clock as an output. The frequency divider includes a logic block to generate a first set of edges of the output clock synchronous with the input clock. The logic block is designed to generate a second set of edges of the output clock synchronous with the output clock of a highest operative frequency-dividing unit in the set.

Design and methods for implementing a Rational Ratio Multiplier (RRM) with close to 50% duty cycle. This invention gives an optimal way to implement an RRM that saves both area and power for a given design and is able to achieve a good accuracy of the output clock with a difference between the high period and the low period of the output clock by only half a cycle of the input clock which is the closest to get to a 50% duty cycle clock.

The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.