An active termination circuit comprising an input node connected to a transmission line, a first transistor, and a second transistor. The transmission line supplies a signal to the input node. The first transistor is diode connected between a high voltage supply and the input node. The first transistor terminates the signal when the signal is at a low logic level. The second transistor is diode connected between the input node and a low voltage supply. The second transistor terminates the signal when the signal is at a high logic level.

A frequency divider circuit includes: a first latch circuit that including: a pair of input transistors each having a gate thereof configured to connect to a signal line to which a first voltage is supplied; and a pair of output nodes, and configured to receive a single-phase clock signal; and a second latch circuit of SR-type, the second latch circuit having a set input thereof and a reset input thereof configured to connect to the pair of output nodes of the first latch circuit, and configured to output differential clock signals of which frequency is half a frequency of the single-phase clock signal. The first latch circuit is configured to perform amplification and reset operations alternately repeatedly in response to the single-phase clock signal.

A frequency divider circuit includes: a first latch circuit that including: a pair of input transistors each having a gate thereof configured to connect to a signal line to which a first voltage is supplied; and a pair of output nodes, and configured to receive a single-phase clock signal; and a second latch circuit of SR-type, the second latch circuit having a set input thereof and a reset input thereof configured to connect to the pair of output nodes of the first latch circuit, and configured to output differential clock signals of which frequency is half a frequency of the single-phase clock signal. The first latch circuit is configured to perform amplification and reset operations alternately repeatedly in response to the single-phase clock signal.

A synchronous divider circuit with time-synchronized outputs. The synchronous divider circuit includes a plurality of divider stages including each a D-flip-flop circuit and a respective retiming flip-flop circuit, wherein an output terminal of the retiming flip-flop circuit of a current divider stage is connected to an input of the D-flip-flop circuit of a next divider stage, and wherein the current divider stage includes an additional retiming flip-flop circuit, wherein the output terminal of the retiming flip-flop circuit of the current divider stage is connected to an input terminal of the additional retiming flip-flop circuit of the current divider stage, so that an output signal of the additional retiming flip-flop circuit of the current divider stage and an output terminal of the retiming flip-flop circuit of the next divider stage are time-synchronized with respect to each other.

An integrated circuit including: a clock generation circuit configured to generate first and second divided clock signals by dividing an external clock signal; and a command generation circuit configured to synchronize and decode an external command signal based on a divided clock signal of the first and second divided clock signals, which is synchronized with a chip select signal.

An integrated circuit including: a clock generation circuit configured to generate first and second divided clock signals by dividing an external clock signal; and a command generation circuit configured to synchronize and decode an external command signal based on a divided clock signal of the first and second divided clock signals, which is synchronized with a chip select signal.

A method includes obtaining a trigger signal directed to a component in a subset of components of an electronic circuit, and activating a clock corresponding with the subset of components of the electronic circuit for a preliminary period in response to the trigger signal. An active period is determined based on the trigger signal. The clock remains active for the active period. One of a timer or counter is initiated for the active period. A limit is defined for the one of the timer or counter. The active period is dynamically extended for a busy period after the one of the timer or counter is initiated. The clock is deactivated following the active period.

A method includes obtaining a trigger signal directed to a component in a subset of components of an electronic circuit, and activating a clock corresponding with the subset of components of the electronic circuit for a preliminary period in response to the trigger signal. An active period is determined based on the trigger signal. The clock remains active for the active period. One of a timer or counter is initiated for the active period. A limit is defined for the one of the timer or counter. The active period is dynamically extended for a busy period after the one of the timer or counter is initiated. The clock is deactivated following the active period.

An event counter circuit can be configured to monitor operation of a system where a moving average register circuit can be configured to store a moving average value updated in each cycle of operation of the system by adding a number of system events occurring during a current cycle of the system operation to either 1) a current moving average value stored in the moving average register circuit or 2) a keep value generated by partitioning the current moving average value into the keep value and a transfer value representing system events not included in a determination of the moving average value for subsequent cycles of operation of the system.

An event counter circuit can be configured to monitor operation of a system where a moving average register circuit can be configured to store a moving average value updated in each cycle of operation of the system by adding a number of system events occurring during a current cycle of the system operation to either 1) a current moving average value stored in the moving average register circuit or 2) a keep value generated by partitioning the current moving average value into the keep value and a transfer value representing system events not included in a determination of the moving average value for subsequent cycles of operation of the system.