Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.

A data reading method is provided. The method includes using X read voltage sets to read a target word line, so as to obtain X read results; in a first order, updating a final Gray code index of each of a plurality of target memory cells of the target word line, and obtaining (X1) abnormal Gray code count sets according to the X read results, wherein an i.sup.th read result among the X read results includes a Gray code corresponding to an i.sup.th read voltage set of each of the target memory cells, and the Gray code corresponds to one of N Gray code indexes; and selecting (N1) optimized read voltages from (X1)*(N1) read voltages of the corresponding (X1) read voltage sets to form an optimized read voltage set according to the obtained (X1) abnormal Gray code count sets.

Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.

A time-to-digital converter arrangement has a ring oscillator with a plurality of inverting elements and a first and a second counter coupled to the ring oscillator. The first counter is configured to increment a first counter value if a positive edge transition is present at one of the inverting elements. The second counter is configured to increment a second counter value if a negative edge transition is present at the one of the inverting elements. A storage element stores the first and the second counter value and logical states of the plurality of inverting elements. A decoder coupled to the storage element selects one of the first and the second counter value as a valid value based on an evaluation of the stored logical states, and outputs a total counter value based on the valid value and the stored logical states.

An A/D conversion device includes a phase-difference clock generation unit configured to use a plurality of phase interpolators to generate multi-phase clock signals, of which phases are shifted with respect to an input clock signal, from the input clock signal and a signal obtained by delaying the input clock signal; and an A/D conversion unit configured to perform A/D conversion on an input analog signal using the multi-phase clock signals generated by the phase-difference clock generation unit.

An N bit counter includes a lower counter having a first output having M bits that operates a first counting frequency. An upper counter having a second output having NM+L bits operates a second counting frequency. The second counting frequency is equal to the first counting frequency divided by 2.sup.(M-L). An error correction controller is coupled to receive the first and second outputs and perform operations that include comparing the L least significant bits (LSBs) of the second output and at least one most significant bit (MSB) of the first output, and correcting the NM MSBs of the second output in response to the comparison. The lower bits of the N bit counter are the M bits of the first output, and the upper bits of the N bit counter are the corrected NM MSBs of the second output.

A counter distribution system includes an N bit counter to receive a first counting clock to generate a plurality of data bits including lower data bits on lower data bit lines and upper data bits on upper data bit lines. The upper data bits include at least one redundant bit to provide error correction for the counter distribution system. A plurality of latches is coupled to the N bit counter. Each one of the lower data bit lines and each one of the upper data bit lines is coupled to at least one of the latches. The latches are arranged into a plurality of groupings of latches. Each grouping of latches is coupled to a respective latch enable signal. Each latch in each grouping of latches is coupled to latch a respective one of the plurality of data bits in response to the respective latch enable signal.

An N bit counter includes a lower counter having a first output having M bits that operates a first counting frequency. An upper counter having a second output having NM+L bits operates a second counting frequency. The second counting frequency is equal to the first counting frequency divided by 2.sup.(ML). An error correction controller is coupled to receive the first and second outputs and perform operations that include comparing the L least significant bits (LSBs) of the second output and at least one most significant bit (MSB) of the first output, and correcting the NM MSBs of the second output in response to the comparison. The lower bits of the N bit counter are the M bits of the first output, and the upper bits of the N bit counter are the corrected NM MSBs of the second output.

A time-to-digital converter arrangement has a ring oscillator with a plurality of inverting elements and a first and a second counter coupled to the ring oscillator. The first counter is configured to increment a first counter value if a positive edge transition is present at one of the inverting elements. The second counter is configured to increment a second counter value if a negative edge transition is present at the one of the inverting elements. A storage element stores the first and the second counter value and logical states of the plurality of inverting elements. A decoder coupled to the storage element selects one of the first and the second counter value as a valid value based on an evaluation of the stored logical states, and outputs a total counter value based on the valid value and the stored logical states.

A power control method and a device are provided. The method includes: modulating a first bit stream by using a first modulation scheme to obtain a first modulation symbol, modulating a second bit stream by using a second modulation scheme to obtain a second modulation symbol, and modulating, by using a third modulation scheme, a combined bit stream obtained by combining the first bit stream and the second bit stream to obtain a joint modulation symbol; modifying the first modulation symbol by using a first modification coefficient to obtain a first modified modulation symbol, and modifying the second modulation symbol by using a second modification coefficient to obtain a second modified modulation symbol; separately performing power control processing on the first modified modulation symbol and the second modified modulation symbol, and sending, to a terminal device, a combined modulation symbol obtained after the power control.