A read clock generation circuit may include a multiplexer selecting one of divided clock signals in response to a selection signal and outputting the selected divided clock signal as a preliminary read clock signal, a detection circuit generating a detection signal for indicating detection timing of a divided clock signal having the fastest second edge after the first edge of a write clock signal, among the divided clock signals, based on a result of a comparison between the phases of the divided clock signals and the phase of the write clock signal, a counter generating the selection signal by counting the detection signal in response to the write clock signal, and a correction circuit outputting, as a read clock signal, a signal from which pulses corresponding to an invalid section have been removed, among the pulses of the preliminary read clock signal, in response to the detection signal.

A read clock generation circuit may include a multiplexer selecting one of divided clock signals in response to a selection signal and outputting the selected divided clock signal as a preliminary read clock signal, a detection circuit generating a detection signal for indicating detection timing of a divided clock signal having the fastest second edge after the first edge of a write clock signal, among the divided clock signals, based on a result of a comparison between the phases of the divided clock signals and the phase of the write clock signal, a counter generating the selection signal by counting the detection signal in response to the write clock signal, and a correction circuit outputting, as a read clock signal, a signal from which pulses corresponding to an invalid section have been removed, among the pulses of the preliminary read clock signal, in response to the detection signal.

The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates. Compared with traditional divide-by-2 frequency division clock circuits based on D-flip-flop, the low-jitter frequency division clock circuit of the present disclosure has fewer logic gates, a shorter delay, and lower jitter.

A transmit signal generator is provided. The transmit signal generator has an n−1 bit comparator having a first set of n−1 input lines and a second set of n−1 input lines and an output line, the n−1 bit comparator operable to compare signals of the first set of n−1 input lines and signals of the second set of n−1 input lines and provide the output of the n−1 bit comparator based on the comparison, and an n-bit binary counter having a clock signal input line, a reset signal input line, a clock enable line connected to the output line of the n−1 bit comparator, and n output lines. One of the n output lines provides a sequence of pulse as an output of the transmit signal generator.

A transmit signal generator is provided. The transmit signal generator has an n−1 bit comparator having a first set of n−1 input lines and a second set of n−1 input lines and an output line, the n−1 bit comparator operable to compare signals of the first set of n−1 input lines and signals of the second set of n−1 input lines and provide the output of the n−1 bit comparator based on the comparison, and an n-bit binary counter having a clock signal input line, a reset signal input line, a clock enable line connected to the output line of the n−1 bit comparator, and n output lines. One of the n output lines provides a sequence of pulse as an output of the transmit signal generator.

A read clock generation circuit may include a multiplexer selecting one of divided clock signals in response to a selection signal and outputting the selected divided clock signal as a preliminary read clock signal, a detection circuit generating a detection signal for indicating detection timing of a divided clock signal having the fastest second edge after the first edge of a write clock signal, among the divided clock signals, based on a result of a comparison between the phases of the divided clock signals and the phase of the write clock signal, a counter generating the selection signal by counting the detection signal in response to the write clock signal, and a correction circuit outputting, as a read clock signal, a signal from which pulses corresponding to an invalid section have been removed, among the pulses of the preliminary read clock signal, in response to the detection signal.

A read clock generation circuit may include a multiplexer selecting one of divided clock signals in response to a selection signal and outputting the selected divided clock signal as a preliminary read clock signal, a detection circuit generating a detection signal for indicating detection timing of a divided clock signal having the fastest second edge after the first edge of a write clock signal, among the divided clock signals, based on a result of a comparison between the phases of the divided clock signals and the phase of the write clock signal, a counter generating the selection signal by counting the detection signal in response to the write clock signal, and a correction circuit outputting, as a read clock signal, a signal from which pulses corresponding to an invalid section have been removed, among the pulses of the preliminary read clock signal, in response to the detection signal.

A transmit signal generator is provided. The transmit signal generator has an n1 bit comparator having a first set of n1 input lines and a second set of n1 input lines and an output line, the n1 bit comparator operable to compare signals of the first set of n1 input lines and signals of the second set of n1 input lines and provide the output of the n1 bit comparator based on the comparison, and an n-bit binary counter having a clock signal input line, a reset signal input line, a clock enable line connected to the output line of the n1 bit comparator, and n output lines. One of the n output lines provides a sequence of pulse as an output of the transmit signal generator.

A transmit signal generator is provided. The transmit signal generator has an n1 bit comparator having a first set of n1 input lines and a second set of n1 input lines and an output line, the n1 bit comparator operable to compare signals of the first set of n1 input lines and signals of the second set of n1 input lines and provide the output of the n1 bit comparator based on the comparison, and an n-bit binary counter having a clock signal input line, a reset signal input line, a clock enable line connected to the output line of the n1 bit comparator, and n output lines. One of the n output lines provides a sequence of pulse as an output of the transmit signal generator.

An improved reference current generator for use in an integrated circuit. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The stable reference current is mirrored and, if desired, amplified for use on the integrated circuit. A driver selectively drives state information off chip for assisting in post-silicon correction of unwanted sensitivities. A configuration memory stores values used to adjust effective device widths and lengths for correcting unwanted sensitivities.