An improved reference current generator for use in an integrated circuit. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The stable reference current is mirrored and, if desired, amplified for use on the integrated circuit. A driver selectively drives state information off chip for assisting in post-silicon correction of unwanted sensitivities. A configuration memory stores values used to adjust effective device widths and lengths for correcting unwanted sensitivities.

The present application relates to a circuit of a frequency divider arranged to divide a frequency of an input clock signal by odd integer N and a method of operating the circuit. A shift register comprises a number of N+1 clock gating cells, which are connected in series to each other, and a shift logic. An input clock signal is fed into clock signal inputs of each one of the number of N+1 clock gating cells. The shift logic is configured to receive enable signals from a set of the number of N+1 clock gating cells and to generate a feedback signal, which is supplied to a gate enable input of the first one of the number of N+1 clock gating cells. A multiplexer is configured to receive at input ports N+1 gated clock signals and to output a rotation clock signal, which has a frequency of 2/N of the frequency of the input clock signal. A frequency generator is configured to receive the rotation clock signal and to generate an output clock signal having a frequency of 1/N.

A method includes loading a clock divider counter with most significant bits (MSBs) of a divider value, decrementing the counter at a same edge of each pulse of a clock signal, and comparing a value contained in the counter to a reference value and generating an end count signal if the value contained in the counter matches the reference value. If the value is even, the reference value is set to 1. If the value is odd, the reference value is set to 1, except for every other assertion of the end count signal, where the reference value is instead set to 0. A toggle signal transitions at a same edge of each pulse of the end count signal. The counter is reloaded with MSBs of the divider value based upon the end count signal. A divided version of the clock signal is generated based upon the toggle signal.

According to an embodiment, a capacitance determination circuit is provided comprising a voltage controlled oscillator configured to generate a frequency signal whose frequency depends on a control voltage supplied to the voltage controlled oscillator, a capacitor coupled to the voltage controlled oscillator wherein the control voltage depends on a voltage across the capacitor and a processing circuit configured to generate, based on the frequency signal generated by the voltage controlled oscillator over a time interval comprising at least one phase in which the capacitor is charged and comprising at least one phase in which the capacitor is discharged, an indication of the capacitance of the capacitor.

According to an embodiment, a capacitance determination circuit is provided comprising a voltage controlled oscillator configured to generate a frequency signal whose frequency depends on a control voltage supplied to the voltage controlled oscillator, a capacitor coupled to the voltage controlled oscillator wherein the control voltage depends on a voltage across the capacitor and a processing circuit configured to generate, based on the frequency signal generated by the voltage controlled oscillator over a time interval comprising at least one phase in which the capacitor is charged and comprising at least one phase in which the capacitor is discharged, an indication of the capacitance of the capacitor.

The present application relates to a circuit of a frequency divider arranged to divide a frequency of an input clock signal by odd integer N and a method of operating the circuit. A shift register comprises a number of N+1 clock gating cells, which are connected in series to each other, and a shift logic. An input clock signal is fed into clock signal inputs of each one of the number of N+1 clock gating cells. The shift logic is configured to receive enable signals from a set of the number of N+1 clock gating cells and to generate a feedback signal, which is supplied to a gate enable input of the first one of the number of N+1 clock gating cells. A multiplexer is configured to receive at input ports N+1 gated clock signals and to output a rotation clock signal, which has a frequency of 2/N of the frequency of the input clock signal. A frequency generator is configured to receive the rotation clock signal and to generate an output clock signal having a frequency of 1/N.

A method includes loading a clock divider counter with most significant bits (MSBs) of a divider value, decrementing the counter at a same edge of each pulse of a clock signal, and comparing a value contained in the counter to a reference value and generating an end count signal if the value contained in the counter matches the reference value. If the value is even, the reference value is set to 1. If the value is odd, the reference value is set to 1, except for every other assertion of the end count signal, where the reference value is instead set to 0. A toggle signal transitions at a same edge of each pulse of the end count signal. The counter is reloaded with MSBs of the divider value based upon the end count signal. A divided version of the clock signal is generated based upon the toggle signal.

A method and apparatus for generating an improved reference voltage for use, for example, in a system requiring accurate low power operation. In particular, our reference voltage generator is adapted to output VREF as a function of the voltage difference between V1 and V2. The reference voltage generator is further adapted to include our reference voltage tuner to compensate for predetermined sensitivities of the reference voltage VREF, and to adjust the absolute value of VREF. During manufacturing and system test, a driver may be used to drive a buffered or unbuffered version of VREF to off-chip test functionality. Also, a configuration memory may be used to store the trim settings during normal operation, and make such settings available to outside resources.

A method and apparatus for generating an improved reference voltage for use, for example, in a system requiring accurate low power operation. In particular, our reference voltage generator is adapted to output VREF as a function of the voltage difference between V1 and V2. The reference voltage generator is further adapted to include our reference voltage tuner to compensate for predetermined sensitivities of the reference voltage VREF, and to adjust the absolute value of VREF. During manufacturing and system test, a driver may be used to drive a buffered or unbuffered version of VREF to off-chip test functionality. Also, a configuration memory may be used to store the trim settings during normal operation, and make such settings available to outside resources.

An improved reference current generator for use in an integrated circuit. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The stable reference current is mirrored and, if desired, amplified for use on the integrated circuit. A driver selectively drives state information off chip for assisting in post-silicon correction of unwanted sensitivities. A configuration memory stores values used to adjust effective device widths and lengths for correcting unwanted sensitivities.