An improved reference current generator for use in an integrated circuit. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The stable reference current is mirrored and, if desired, amplified for use on the integrated circuit. A driver selectively drives state information off chip for assisting in post-silicon correction of unwanted sensitivities. A configuration memory stores values used to adjust effective device widths and lengths for correcting unwanted sensitivities.

An improved reference current generator for use in an integrated circuit. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The stable reference current is mirrored and, if desired, amplified for use on the integrated circuit. A driver selectively drives state information off chip for assisting in post-silicon correction of unwanted sensitivities. A configuration memory stores values used to adjust effective device widths and lengths for correcting unwanted sensitivities.

A synthesizer module arranged to generate a timing signal. The synthesizer module comprises an odd-numbered frequency divider circuit arranged to receive a reference timing signal and to output at least one frequency-divided signal having a frequency equal to 1/M times the frequency of the reference timing signal, where M is an odd-numbered integer. A 90 phase-shift component is arranged to receive the reference timing signal and to output a 90 phase-shifted form of the reference timing signal. A re-timing circuit is arranged to re-time a set of transitions of the frequency-divided signal to be temporally aligned to transitions of the 90 phase-shifted form of the reference timing signal to generate the timing signal comprising the re-timed transitions of the frequency-divided signal.

Embodiments relate to an accumulator-based phase memory. An aspect includes a phase correction calculator configured to, based on receipt of a new frequency tuning word on a frequency tuning word input, determine a phase difference between the new frequency tuning word and a current frequency tuning word, and determine a product of the phase difference and a value of a counter. Another aspect includes wherein the accumulator-based phase memory determines a phase offset value based on the product of the phase difference and the value of the counter. Another aspect includes the accumulator-based phase memory further comprising a waveform generator configured to generate a waveform based on the new frequency tuning word and the phase offset value.

A digital control oscillator circuit includes: a ring oscillator having delay elements delaying a pulse signal; a counter circuit counting the circulation number of the pulse signal; a rough period generation unit acquiring a period setting value as a magnification ratio for a reference clock, and counting the reference clock using an integer part of the ratio to generate a rough period timing; a fraction conversion unit converting a decimal point part of the ratio into the number of the elements passed by the pulse signal to generate a fraction; and an output processing unit selecting a timing when outputs of the ring oscillator and the counter circuit become values corresponding to the fraction as an output timing when a time corresponding to the fraction has passed after the rough period timing, and generating an output signal oscillating at a period represented by the period setting value according to the output timing.

An electronic device includes a control logic portion suitable for generating a hold control signal based on a count enable signal, and a counting portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and a counting clock signal.

An electronic device includes a control logic portion suitable for generating a hold control signal based on a count enable signal, and a counting portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and a counting clock signal.

An electronic device includes a control logic portion suitable for generating a hold control signal based on a count enable signal, and a counting portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and a counting clock signal.

An electronic device includes a control logic portion suitable for generating a hold control signal based on a count enable signal, and a counting portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and a counting clock signal.

An electronic device includes a control logic portion suitable for generating a hold control signal based on a count enable signal, and a counting portion suitable for performing a counting operation while a latch operation stops during a counting section and performing the latch operation while the counting operation stops during a holding section based on the hold control signal and a counting clock signal.