A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.

There is disclosed configurable frequency-divider circuitry for generating a target signal of a frequency Fr/Di based on a reference signal of a frequency Fr, where Di is an integer divider ratio, the frequency-divider circuitry comprising: N divider stages organised into a ring, each stage configured to receive an input signal and generate an output signal, with the output signal of each successive stage in the ring being the input signal of the next stage in the ring, wherein: the ring of stages is controlled by the reference signal so that the output signals are governed by the reference signal; the target signal is one of the output signals or a signal derived therefrom; and at least one of the stages is a configurable stage, whose mode of operation is configurable based on a configuration signal to configure the value of Di.

A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.

A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

There is disclosed configurable frequency-divider circuitry for generating a target signal of a frequency Fr/Di based on a reference signal of a frequency Fr, where Di is an integer divider ratio, the frequency-divider circuitry comprising: N divider stages organised into a ring, each stage configured to receive an input signal and generate an output signal, with the output signal of each successive stage in the ring being the input signal of the next stage in the ring, wherein: the ring of stages is controlled by the reference signal so that the output signals are governed by the reference signal; the target signal is one of the output signals or a signal derived therefrom; and at least one of the stages is a configurable stage, whose mode of operation is configurable based on a configuration signal to configure the value of Di.

A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit

A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

A clock divider includes, in part, a pair of counters and a programmable delay line. A first one of the counters operates at a first frequency and is configured to count using a first integer portion of the divisor. The second counter operates at a second frequency smaller than the first frequency and is configured to count using a second integer portion of the divisor. The programmable delay includes, in part, a chain of delay elements configured to generate a multitude of delays at the output of the second counter. A multiplexer selects one of the generated delays in accordance with the fractional portion of the divisor. The second counter increases its count only when the first counter reaches a terminal count. The first and second integer portions are loaded respectively into the first and second counters when the second counter reaches its terminal count.

A clock divider includes, in part, a pair of counters and a programmable delay line. A first one of the counters operates at a first frequency and is configured to count using a first integer portion of the divisor. The second counter operates at a second frequency smaller than the first frequency and is configured to count using a second integer portion of the divisor. The programmable delay includes, in part, a chain of delay elements configured to generate a multitude of delays at the output of the second counter. A multiplexer selects one of the generated delays in accordance with the fractional portion of the divisor. The second counter increases its count only when the first counter reaches a terminal count. The first and second integer portions are loaded respectively into the first and second counters when the second counter reaches its terminal count.

A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.