A frequency divider includes a multiplexer having a first input terminal coupled to receive a first value M and a second input terminal for receiving a second value that is M+LSB, the multiplexer is configured to alternately output the first value M and the second value. The frequency divider includes a multi-modulus divider coupled to the multiplexer for receiving the output of the multiplexer, the multi-modulus divider operable to alternately generate an output pulse at M input clock cycles and at M+LSB clock cycles. A divide-by-two counter having an input coupled to the output of the multi-modulus divider, is operable to divide the output of the multi-modulus divider to generate a divided clock signal having a frequency of N, where N is equal to 2M+LSB. Duty cycle correction logic is coupled to the output of the divide-by-two counter and is configured to correct the duty cycle of the divided clock signal to a fifty percent duty cycle when N is odd.

Systems and methods for controlling a frequency of a clock signal by selectively swallowing pulses in the clock signal are described herein. In one embodiment, a method for adjusting a frequency of a clock signal comprises receiving the clock signal, and swallowing pulses in the clock signal according to a repeating clock-swallowing pattern, wherein the pattern is defined by a sequence of numbers.

In a clock generating circuit, a variable frequency division circuit generates a variable divided clock by dividing a source clock in accordance with a division ratio setting signal. A first clock synchronization circuit generates a first delayed clock that is delayed by a maximum number of clocks from the variable divided clock in synchronization with the source clock and supplies the first delayed clock to a control circuit. One or more second clock synchronization circuits generate one or more second delayed clocks, each of which is delayed by the maximum number of clocks from the variable divided clock in synchronization with the source clock, and supply each of the one or more second delayed clocks to each of one or more functional modules.

A correction arithmetic circuit disclosed herein includes an offset temperature characteristic correction unit that corrects an offset temperature characteristic of an input signal according to an input signal characteristic at a specific temperature and a temperature characteristic at a specific input signal. A signal processor disclosed herein includes a pulse count number setting circuit that generates a pulse count number setting signal in accordance with an input signal and a pulse generation unit that generates a pulse signal by counting a pulse number of a reference clock signal according to the pulse count number setting signal. The pulse count number setting circuit corrects the pulse count number setting signal so as to cancel a frequency temperature characteristic of the pulse signal.

A clock generation device generates a clock signal which has a predetermined number of clocks for each predetermined time in such a way that a clock signal (32.768 kHz+ ( is zero or a positive number)) is input and some clocks of the clock signal are masked.

A processing device according to an aspect of the present disclosure includes: a toggle signal reception circuit configured to receive a toggle signal a value of which transitions between binary values at a timing of a pulse of a frequency-divided clock signal in which a periodic pattern signal is repeated, pulses of the periodic pattern signal being generated by masking predetermined pulses of a mask pulse number among consecutive pulses of a periodic pulse number in an input clock signal, the mask pulse number being smaller than the periodic pulse number; and a communication circuit configured to communicate with another processing device operated by the frequency-divided clock signal at the timing of the pulse of the frequency-divided clock signal among the pulses of the input clock signal, the timing of the pulse of the frequency-divided clock signal being specified using the toggle signal.