A clock generator for generating a target clock with a frequency equal to the frequency of an input clock divided by a non-integer ratio is disclosed. The clock generator comprises a clock divider. The clock divider is configured to divide the input clock by a first dividing ratio during a first portion of a frame period to generate a first clock slower than the target clock, and divide the input clock by a second dividing ratio during a second portion of the frame period to generate a second clock faster than the target clock. A difference between the first dividing ratio and the second dividing ratio is 0.5 or 1. In some embodiments, the first dividing ratio and the second dividing ration are integers closest to the non-integer ratio.

An electronic circuit arranged to receive an oscillating signal and output an output signal at a frequency having a frequency relation with the oscillating signal defined by a divide ratio is provided. The electronic circuit comprises a first frequency divider arranged to receive the oscillating signal and output N frequency divided signals of different phases, a second frequency divider arranged to receive one of the N signals and frequency divide the received signal by a value given by a first control signal provided to the second frequency divider, N latch circuits each being arranged to receive a respective one of the N signals at a clocking input of the respective latch circuit and to receive an output of the second frequency divider at an input of the respective latch circuit, a multiplexer circuit arranged to receive outputs of the N latch circuits and to output a signal, on which the output signal is based, selected from the received signals based on a second control signal provided to the multiplexer circuit, and a control circuit arranged to provide the first control signal and the second control signal based on the divide ratio. A phase-locked loop circuit, a transceiver circuit, a radio station, and a method of frequency dividing an oscillating signal are also provided.

In accordance with an embodiment, a circuit includes an input clock terminal, an output clock terminal, a first input data terminal, and a set of input data terminals having a number of terminals. A divide-by-two block is coupled to the output clock terminal. A modular one-shot clock divider is coupled between the input clock terminal and the divide-by-two block. The modular one-shot clock divider is further coupled to the set of input data terminals. An intermediate clock generation block is coupled between the input clock terminal and the modular one-shot clock divider. The intermediate clock generation block includes a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider. The first digital logic block is further coupled to the first input data terminal, and a clock-blocking block is coupled between the divide-by-two block and the first digital logic block.

Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.

A clock generator for generating a clock equivalent to a target clock which is an input clock divided by a non-integer ratio is disclosed. The clock generator comprises a clock divider configured to receive the input clock and divide the input clock with a reconfigurable dividing ratio; and a control circuit controlling operations of the clock divider to divide the input clock by a first dividing ratio to generate a first number of cycles of a first clock in a frame, and divide the input clock by a second dividing ratio to generate a second number of cycles of a second clock in the frame, wherein a difference between a period of the frame and a cumulative time of the first number of cycles of the first clock and the second number of cycles of the second clock is less than a threshold value.

According to an embodiment, a regulator includes: a voltage control circuit to supply a voltage; a clock signal output circuit to output a clock signal controlled by the voltage supplied from the voltage control circuit; and a current control circuit to supply the voltage supplied from the voltage control circuit to the clock signal output circuit, the current control circuit make to flow a dummy current which is determined based on the voltage, and stopping flowing the dummy current at a timing when the clock signal output circuit outputs the clock signal.

According to an embodiment, a regulator includes: a voltage control circuit to supply a voltage; a clock signal output circuit to output a clock signal controlled by the voltage supplied from the voltage control circuit; and a current control circuit to supply the voltage supplied from the voltage control circuit to the clock signal output circuit, the current control circuit make to flow a dummy current which is determined based on the voltage, and stopping flowing the dummy current at a timing when the clock signal output circuit outputs the clock signal.

A method of dividing a clock signal by an input signal of N bits with M most significant bits is described herein. The method includes dividing the clock signal by the most significant bits of the input signal 2.sup.N-M1 times out of 2.sup.N-M divisions of the clock signal, using a divider. The clock signal is divided by a sum of the most significant bits and the least significant bits one time out of 2.sup.N-M divisions of the clock signal, using the divider. The clock signal is also divided by 2.sup.N-M, 2.sup.N-M times, using the divider.

In many embodiments of the invention, a clock generation circuit includes a numerically controlled oscillator to receive a frequency control word and generate a fractional time signal, a variable delay circuit including a buffer driving a variable switch-capacitor network, the variable delay circuit configured to receive the fractional time signal and generate a delayed clock signal with a time delay that is linear with total capacitance at a load using probabilistic delay assignment, and a probabilistic delay assignment circuit to select between a first delay setting including delay line only and a second delay setting including a sample clock period delay plus delay line, wherein the probabilistic delay assignment circuit assigns probabilities p1=m1/L and p2=(Lm1)/L for selecting the first and second delay settings, where m1 represents a fractional portion of a desired delay and L represents a ratio between sample clock period and unit delay.

In many embodiments of the invention, a clock generation circuit includes a numerically controlled oscillator to receive a frequency control word and generate a fractional time signal, a variable delay circuit including a buffer driving a variable switch-capacitor network, the variable delay circuit configured to receive the fractional time signal and generate a delayed clock signal with a time delay that is linear with total capacitance at a load using probabilistic delay assignment, and a probabilistic delay assignment circuit to select between a first delay setting including delay line only and a second delay setting including a sample clock period delay plus delay line, wherein the probabilistic delay assignment circuit assigns probabilities p1=m1/L and p2=(Lm1)/L for selecting the first and second delay settings, where m1 represents a fractional portion of a desired delay and L represents a ratio between sample clock period and unit delay.