Disclosed herein is a temperature compensated crystal oscillator, TCXO, comprising: a crystal oscillator arrangement configured to generate an output signal of the temperature compensated crystal oscillator; and a temperature sensor arranged to generate a temperature sensor signal, wherein the output signal of the crystal oscillator arrangement is controlled in dependence on the temperature sensor signal; wherein: the temperature sensor comprises a plurality of transistor circuits; each transistor circuit comprises a transistor and a bias circuit; each transistor circuit is arranged to output a temperature signal that is dependent on the temperature of the transistor comprised by the transistor circuit; each bias circuit is configured such that the noise level in each output temperature signal is low; and the plurality of transistor circuits are arranged so that the temperature sensor signal is dependent on each of the plurality of output temperature signals.

The present invention provides a temperature-compensated crystal oscillator based on digital circuit, a closed-loop compensation architecture is employed to realize the high precision compensation of the crystal oscillator. The output frequency f(T) of the TCXO to be compensated is directly connected with the compensation voltage V.sub.c(T) in real time, and the compensation voltage is fed back to the voltage control terminal of the VCXO to be compensated to compensate, so that the output frequency after compensation is equal to the target frequency signal, thus avoiding the frequency shift of output signal caused by temperature hysteresis, i.e. the discrepancy between the temperature acquired by a temperature senor and the real temperature of the resonant wafer in the prior art.

An oscillator includes: a resonator; an oscillation circuit configured to oscillate the resonator; a first temperature compensation circuit configured to perform a first temperature compensation processing of temperature-compensating for a frequency of a first clock signal generated by oscillation of the resonator by the oscillation circuit; and a second temperature compensation circuit configured to receive the first clock signal subjected to the first temperature compensation processing, and to output a second clock signal subjected to a second temperature compensation processing based on the first clock signal. The first temperature compensation circuit is configured to perform a first-order first temperature compensation processing as the first temperature compensation processing. The second temperature compensation circuit is configured to perform a high-order second temperature compensation processing as the second temperature compensation processing.

A compensation apparatus including a primary circuit and a compensation circuit is provided. The primary circuit provides a first voltage, a second voltage, and a first current flowing through a first inductor. The primary circuit includes the first inductor and a function circuit generating an input signal. The first inductor is coupled between a first terminal with the first voltage and a second terminal with the second voltage. The compensation circuit includes a second inductor and a current source circuit. The second inductor is coupled between a third terminal with a third voltage and a fourth terminal with a fourth voltage. The current source circuit outputs a second current flowing through the second inductor. The current source circuit adjusts a frequency of the input signal. The primary circuit and the compensation circuit are coupled via the first inductor and the second inductor.

An oscillator includes a container, an oscillation element housed in the container, a heating circuit housed in the container, and adapted to control a temperature of the oscillation element, a temperature detection circuit housed in the container, a temperature control circuit housed in the container, and adapted to control the heating circuit based on an output of the temperature detection circuit, at least one connecting wire housed in the container, and electrically connects a ground of the temperature detection circuit and a ground of the temperature control circuit to each other, and a ground external terminal disposed on an outer surface of the container, and electrically connected to the ground of the temperature detection circuit and the ground of the temperature control circuit.

A slow-clock calibration method, a slow-clock calibration unit, a clock circuit and a mobile communication terminal are provided. The calibration method includes: obtaining a current temperature of the crystal; searching a unique frequency-divide coefficient corresponding to the current temperature from a preset data base; if the coefficient is found in the data base, inputting the unique coefficient into a frequency divider; if the coefficient is not found in the data base, obtaining an actual sleep length of the mobile communication terminal, if the actual sleep length is not equal to a required sleep length, calculating a required frequency-divide coefficient and updating the data base with the required frequency-divide coefficient, and if the actual sleep length of the mobile communication terminal is equal to the required sleep length, updating the data base with a current frequency-divide coefficient. Accordingly, slow-clock calibration is realized with reduced crystal costs.

A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance.

A circuit device includes a phase comparator that performs phase comparison between an input signal based on an oscillation signal and a reference signal, a processor that performs a digital signal process on phase comparison result data which is a result of the phase comparison so as to generate frequency control data, and an oscillation signal generation circuit that generates the oscillation signal having an oscillation frequency which is set on the basis of the frequency control data. The processor performs the digital signal process by using data used when a hold-over state is ended in a case where the hold-over state occurs due to the absence or the abnormality of the reference signal, and then the hold-over state is ended.

A circuit device includes a phase comparator that performs phase comparison between an input signal based on an oscillation signal and a reference signal, a processor that performs a signal process, and an oscillation signal generation circuit that generates the oscillation signal having an oscillation frequency which is set on the basis of frequency control data from the processor. The circuit device also includes at least one of a first register that stores phase comparison result data, a second register in which one of offset adjustment data for GPS and offset adjustment data for UTC is set, and a third register in which offset adjustment data for adjusting a phase difference is set.

A circuit device includes a phase comparator that performs phase comparison between an input signal based on an oscillation signal and a reference signal, a processor that performs a signal process on frequency control data based on a result of the phase comparison, and an oscillation signal generation circuit that generates the oscillation signal having an oscillation frequency which is set on the basis of frequency control data having undergone the signal process. The phase comparator includes a counter that performs a count operation by using the input signal, and performs the phase comparison by comparing a count value in the counter inn (where n is an integer of 2 or more) cycles of the reference signal with an expected value of the count value in integers.