In-package temperature is controlled with higher accuracy. To this end, a temperature control circuit includes a temperature sensor arranged in a package and detecting temperature in the package, a heater current detection circuit detecting a driving amount of a heater, a target temperature generation circuit generating a target temperature from an intended temperature of a resonator and a detection value of the driving amount detected by the heater current detection circuit, a heater current driver controlling the heater so that the detection temperature detected by the temperature sensor coincides with the target temperature, and an Nth-order correction circuit receiving the detection value of the driving amount detected by the heater current detection circuit or a signal based on the target temperature and cancelling influence of a second or higher order fluctuation component generated in the heater current detection circuit on temperature of the resonator.

A resonance frequency detector has an adder that adds a correction term to an oscillation frequency of an output signal of an oscillator, and detects a predetermined resonance frequency of a resonance element. The correction term is generated based on a phase error in a phase locked loop and a degree of change in phase at the resonance frequency, and the phase locked loop generates a control signal based on the phase error between an output signal of the resonance element that resonates at the resonance frequency and the output signal of the oscillator that varies the oscillation frequency according to the control signal.

A control system for a digitally controlled oscillator with temperature compensation including a loop detector providing an error value, filter circuitry providing a lower resolution digital value to the DCO to generate an output oscillation signal at a frequency within a lower resolution range, tracking circuitry holding a tracking digital value at a tracking offset from center of a tracking range while the lower resolution digital value is being determined, and then regulating the frequency within a higher resolution range by adjusting the tracking digital value, temperature compensation circuitry performing temperature compensation steps to maintain the tracking digital value between first and second thresholds within the predetermined tracking range, and a controller configured to set the first and second thresholds within a narrow range around the tracking offset during a standard operating mode, and to adjust one or both thresholds within a wide range during a critical operating mode.

The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.

A digital phase-locked loop has a digitally controlled oscillator with a first coarse tuning field for coarse tuning of the oscillator frequency, a second coarse tuning field for tuning of the oscillator frequency at finer intervals than the first coarse tuning field, and a fine tuning field for tuning the oscillator to an output frequency at finer intervals than the second coarse tuning field. The second coarse tuning field provides open loop tuning and is linear and connected parallel to the first coarse tuning field. The second coarse tuning field provides wide field temperature compensation and frequency error determination at start up based on an interpolated frequency value obtained prior to start up. Faster settling is provided with less complex algorithms.

A system for performing a phase control operation includes: an internal clock generation circuit configured to generate an internal clock by delaying a clock by a first delay variation, and generate a reference clock by delaying the clock by a second delay variation, wherein the internal clock generation circuit generates the internal clock by delaying the clock by the first delay variation which is controlled according to a phase difference between the internal clock and the reference clock; and a data input/output circuit configured to input/output data in synchronization with the internal clock.

An oscillation circuit includes: a power supply generation module, configured to generate a positive temperature coefficient voltage based on a positive temperature coefficient current; and an oscillator, the positive temperature coefficient voltage serving as a power supply of the oscillator. The oscillator includes: a first ring topological structure, formed by a plurality of first inverters connected end to end and configured to transmit an oscillation signal at a first transmission speed; and a second ring topological structure, formed by a plurality of second inverters connected end to end and configured to transmit the oscillation signal at a second transmission speed. The first ring topological structure is electrically connected with the second ring topological structure, and the second transmission speed is less than the first transmission speed.

A semiconductor integrated circuit includes: a node to receive a reference clock signal; a voltage-controlled oscillation circuit to generate a clock signal based on a code corresponding to a frequency of the reference clock signal received by the node and on a control voltage; a calibration circuit to generate the code based on the frequency of the reference clock signal and on a frequency of the clock signal, and supply the generated code to the voltage-controlled oscillation circuit; and a phase locked loop circuit to generate the control voltage based on a phase difference of the clock signal with respect to the reference clock signal, and supply the generated control voltage to the voltage-controlled oscillation circuit. The voltage-controlled oscillation circuit is capable of changing the frequency of the clock signal based on the code supplied from the calibration circuit and on the control voltage supplied from the phase locked loop circuit.

A system for performing a phase control operation includes: an internal clock generation circuit configured to generate an internal clock by delaying a clock by a first delay variation, and generate a reference clock by delaying the clock by a second delay variation, wherein the internal clock generation circuit generates the internal clock by delaying the clock by the first delay variation which is controlled according to a phase difference between the internal clock and the reference clock; and a data input/output circuit configured to input/output data in synchronization with the internal clock.

System and method for temperature-calibration of a crystal oscillator (XO) in a mobile device. A temperature-calibration status of the XO is determined and a trigger condition related to temperature-calibration of the XO is detected. If the temperature-calibration status of the XO is not fully temperature-calibrated or if the XO has not been previously temperature-calibrated, a temperature-calibration session is initiated by an XO manager based on the condition, wherein a receiver is configured to receive signals and temperature-calibration of the XO is performed in a background mode based on the received signals. The condition based triggering ensures that the XO is temperature-calibrated prior to launch of any position based or global navigation satellite systems (GNSS) based applications on the mobile device. The trigger condition can include first use or power-on, charging, presence in an outdoor environment, variation in operating temperature, pre-specified time, and/or user input pertaining to the mobile device.