An oscillator includes: a resonator; a heat generation circuit configured to heat the resonator; a temperature sensor positioned closer to the heat generation circuit than the resonator is and configured to output a temperature detection signal; a temperature control circuit configured to output a temperature control signal for controlling a temperature of the heat generation circuit based on the temperature detection signal; an oscillation clock signal output circuit configured to oscillate the resonator and output an oscillation clock signal; and a correction circuit configured to correct a frequency variation of the oscillation clock signal, in which the correction circuit is configured to compensate for a transient frequency variation of the oscillation clock signal based on a time change amount of the temperature detection signal or a time change amount of the temperature control signal.

A variable-frequency oscillator generates an oscillator clock having a frequency that corresponds to a control signal. A programmable frequency divider divides the oscillator clock, so as to generate a divided clock. A F/V converter circuit includes a capacitor and a switch that switches at a frequency that corresponds to the divided clock, and generates a detection voltage that corresponds to a reference current. A reference voltage source outputs a reference voltage that corresponds to the electric potential that occurs at the resistor due to a reference current. A feedback circuit adjusts a control signal such that the detection voltage approaches the reference voltage. A correction circuit changes the frequency-dividing ratio of the programmable frequency divider based on a modulation signal modulated according to a correction coefficient that corresponds to the temperature.

A performance calculation method suitable for a chip is provided. The chip includes oscillator circuit systems configured to generate oscillation signals and to sense operation states of the chip to adjust periods of the oscillation signals. The method includes following operations: when the chip is in a first operation state, constructing a first function according to the periods of the oscillation signals and a first performance value of the chip; when the chip is in a second operation state, constructing a second function according to the periods of the oscillation signals and a second performance value of the chip; adjusting coefficients of the first or second function according to trajectories of graphs of the first and second functions, so that the graphs of the first and second functions intersect at a coordinate point; constructing a performance function of the chip according to the first and second functions.

Temperature compensated oscillators are provided. The oscillator comprises an oscillator circuit and a temperature compensation module. The temperature compensation module reduces temperature induced errors in the frequency of oscillation of the oscillator by providing a temperature compensation signal to the oscillator circuit based on a temperature sensor output. The temperature compensation module comprises a low pass filter configured to reduce noise in the temperature compensation signal. The low pass filter is such that, using Laplace representations of transfer functions, the transfer function H(s) of the filter is equivalent to the transfer function of a closed loop configuration in which a module having an open loop transfer function G(s) is configured to generate an output from the closed loop configuration by applying the open loop transfer function G(s) to an error between an input to the closed loop configuration and the output from the closed loop configuration.

Systems and methods for digital synthesis of an output signal using a frequency generated from a resonator and computing amplitude values that take into account temperature variations and resonant frequency variations resulting from manufacturing variability are described. A direct frequency synthesizer architecture is leveraged on a high Q resonator, such as a film bulk acoustic resonator (FBAR), a spectral multiband resonator (SMR), and a contour mode resonator (CMR) and is used to generate pristine signals.

An embodiment of the present disclosure relates to a device comprising an electronic circuit; an oscillation circuit comprising a quartz crystal, configured to provide a clock signal to the electronic circuit; and a heater configured to increase the temperature of the quartz crystal.

The present disclosure relates to a method for controlling a device comprising an oscillation circuit, configured to provide a clock signal to a radio frequency circuit, and an antenna, in which the enabling of the passage of the signal from the circuit to the antenna is delayed with respect to an instant from which a power amplifier of the circuit is enabled.

The present disclosure relates to an electronic device comprising a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.

An oscillation circuit includes a first oscillation circuit configured to oscillate a resonator to generate a first oscillation signal, a second oscillation circuit configured to generate a second oscillation signal, a frequency measurement circuit configured to measure a frequency of the second oscillation signal based on the first oscillation signal in a first period in which the first oscillation circuit is in operation, a holding circuit configured to hold a measurement result by the frequency measurement circuit in a second period in which the first oscillation circuit is not in operation, and an oscillation signal generation circuit configured to generate a third oscillation signal based on the second oscillation signal and the measurement result held in the holding circuit in a third period in which the first oscillation circuit starts up, wherein the third oscillation signal is supplied to the first oscillation circuit in the third period.

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.