The present invention relates to passive phased injection locked circuit and ring-based voltage controlled oscillators. passive phased injection locked circuit comprises first and second transmission lines, each has a plurality of discrete elements, that are operative to deley the phase of AC signal. Between the first and second transmission lines, a capacitor network is formed to advance the phases of the AC signal in concert along the transmission lines. For the ring-based voltage controlled oscillators, each of the first and second transmission lines has an odd number of discrete elements.

Disclosed are methods and apparatuses for reducing fractional spurs in an All-Digital Phase Lock Loop (ADPLL). An exemplary apparatus includes a crystal oscillator configured to generate a first frequency reference signal, a non-integer divider coupled to the crystal oscillator and configured to divide the first frequency reference signal by a non-integer variable to generate a second frequency reference signal, and a multiplexor coupled to the non-integer divider and the crystal oscillator and configured to output the first frequency reference signal or the second frequency reference signal to the ADPLL, wherein the multiplexor is configured to output the second frequency reference signal based on the ADPLL being tuned to a low fractionality channel.

An integrated circuit package includes an interposer with an embedded clock network formed by multiple clock trees. A die with first and second clock circuits is disposed over the interposer. At least one of the first and second clock trees is a resonant clock tree and both the first and second clock circuits may provide clock signals at different frequencies. The first clock circuit may provide clock signals at one frequency to a clock tree in the embedded clock network while the second clock circuit may provide clock signals at another frequency to another clock tree in the embedded clock tree network.

An integrated circuit package includes an interposer with an embedded clock network formed by multiple clock trees. A die with first and second clock circuits is disposed over the interposer. At least one of the first and second clock trees is a resonant clock tree and both the first and second clock circuits may provide clock signals at different frequencies. The first clock circuit may provide clock signals at one frequency to a clock tree in the embedded clock network while the second clock circuit may provide clock signals at another frequency to another clock tree in the embedded clock tree network.

A frequency control device is provided. The frequency control device is configured to receive a plurality of environmental state parameters of an environment; and convert the plurality of environmental state parameters to an environmental state vector. The frequency control device is also configured to receive the environmental state vector and a search request from a filter bank device communicatively coupled to the frequency control device, the search request being triggered by a power level of a radio frequency (RF) signal at an input or an output of the filter bank device; and determine, based on the environmental state vector, a control signal corresponding to a configuration of disabling a selected filter in a plurality of filters in the filter bank device to attenuate the RF signal in the input of the filter bank device.

A frequency control device is provided. The frequency control device is configured to receive a plurality of environmental state parameters of an environment; and convert the plurality of environmental state parameters to an environmental state vector. The frequency control device is also configured to receive the environmental state vector and a search request from a filter bank device communicatively coupled to the frequency control device, the search request being triggered by a power level of a radio frequency (RF) signal at an input or an output of the filter bank device; and determine, based on the environmental state vector, a control signal corresponding to a configuration of disabling a selected filter in a plurality of filters in the filter bank device to attenuate the RF signal in the input of the filter bank device.