Multiple, distributed, clock generating delay-locked loop (DLL) elements are interconnected/coupled in such a way as to reduce the amount of phase error present in the clocks output by these DLL elements. A plurality of DLL elements are interconnected/coupled such that a root input clock is successively relayed down a series of DLL elements. The output clocks from each of these DLL elements are interconnected/coupled to phase-corresponding output clocks from DLL elements in the series. This reduces the amount of phase error on these output clocks when compared to DLL elements that do not have outputs coupled to each other.

A clock generation circuit may include a clock receiver, a first delay loop circuit, and a second delay loop circuit. The clock receiver may receive a first clock signal and a second clock signal and generate a first reception clock signal and a second reception clock signal. The first delay loop circuit may receive the first reception clock signal and the second reception clock signal generate a reference clock signal. The first delay loop circuit may perform a delay-locking operation on the reference clock signal to generate a first delay locked clock signal. The second delay loop circuit may delay the first reception clock signal and the second reception clock signal based on the first delay locked clock signal and an internal clock signal to generate a first internal clock signal.

A clock generation circuit may include a clock receiver, a first delay loop circuit, and a second delay loop circuit. The clock receiver may receive a first clock signal and a second clock signal and generate a first reception clock signal and a second reception clock signal. The first delay loop circuit may receive the first reception clock signal and the second reception clock signal generate a reference clock signal. The first delay loop circuit may perform a delay-locking operation on the reference clock signal to generate a first delay locked clock signal. The second delay loop circuit may delay the first reception clock signal and the second reception clock signal based on the first delay locked clock signal and an internal clock signal to generate a first internal clock signal.

The present disclosure discloses an on-chip synchronous self-repairing system based on a low-frequency reference signal. The system adopts a dual-input PLL stellate coupled structure or a dual-input PLL butterfly-shaped coupled structure, and delay of the whole loop is made to be an integral multiple of the reference signal by synchronizing the transmitted reference signal with the received reference signal, so as to ensure synchronization of local oscillation signal of each IC chip. The transmission wire based on an adjustable left-handed material is used as a delay wire to connect the dual-input PLL, thereby achieving low loss and reducing the physical distance of the delay wire. The system has the advantages of small area, low loss, strong adaptability and strict synchronization in various environments.

The present disclosure discloses an on-chip synchronous self-repairing system based on a low-frequency reference signal. The system adopts a dual-input PLL stellate coupled structure or a dual-input PLL butterfly-shaped coupled structure, and delay of the whole loop is made to be an integral multiple of the reference signal by synchronizing the transmitted reference signal with the received reference signal, so as to ensure synchronization of local oscillation signal of each IC chip. The transmission wire based on an adjustable left-handed material is used as a delay wire to connect the dual-input PLL, thereby achieving low loss and reducing the physical distance of the delay wire. The system has the advantages of small area, low loss, strong adaptability and strict synchronization in various environments.

A third signal having a phase intermediate between a first signal based on a reference signal and a second signal with a phase shifted by an element of a previous stage is generated, a signal obtained by shifting the phase of the third signal by a first phase shill amount is output as a second signal to an element of a subsequent stage, a phase difference between the third signal and a fourth signal obtained by shifting the phase of a first signal output from the element of the subsequent stage by the first phase shift amount is detected, and the first phase shift amount is controlled on the basis of the detected phase difference.

A delay locked loop circuit includes a first delay locked loop and a second delay locked loop having different characteristics. The first delay locked loop performs a delay-locking operation on a reference clock signal to generate a delay locked clock signal. The second delay locked loop performs a delay-locking operation on the delay locked clock signal to generate an internal clock signal.

A clock and data recovery (CDR) system may use one or more clock signals in sync with recovered data rate. By accumulating a dithering tuning counter value at a data oversampling rate, a plurality of single bit signals at multiples of the recovered data rate and in sync with the recovered data rate can be accurately generated while utilizing the full range of the accumulator. This plurality of clock signals can be used in various modules in the CDR system and other modules in a transceiver system incorporating the CDR system.

A clock and data recovery (CDR) system may use one or more clock signals in sync with recovered data rate. By accumulating a dithering tuning counter value at a data oversampling rate, a plurality of single bit signals at multiples of the recovered data rate and in sync with the recovered data rate can be accurately generated while utilizing the full range of the accumulator. This plurality of clock signals can be used in various modules in the CDR system and other modules in a transceiver system incorporating the CDR system.

A clock generation circuit may be provided. The clock generation circuit may include a master DLL (Delay Locked Loop) circuit, a code divider and a slave DLL circuit. The master DLL may generate a phase pulse signal having a pulse width corresponding to one cycle of a clock signal, and may generate a delay control code corresponding to the phase pulse signal. The code divider may generate a divided delay control code corresponding to a predetermined time by dividing the delay control code. The slave DLL circuit may generate a delayed strobe signal by delaying a strobe signal according to the divided delay control code.