An audio processing apparatus and an audio processing method for dynamically adjusting an audio clock are provided. The audio processing apparatus includes a first interface, a buffer, a clock generator, a processor, and a second interface. The first interface receives audio data from the host. The buffer stores the audio data to generate a first audio packet and determines relationships between a data volume of the first audio packet and a first upper threshold and a first lower threshold. The second interface outputs the first audio packet and a clock signal to a codec apparatus. In response to the data volume of the first audio packet being less than the first lower threshold, the buffer outputs an underflow interrupt signal. In response to the data volume of the first audio packet being greater than the first upper threshold, the buffer outputs an overflow interrupt signal.

An audio processing apparatus and an audio processing method for dynamically adjusting an audio clock are provided. The audio processing apparatus includes a first interface, a buffer, a clock generator, a processor, and a second interface. The first interface receives audio data from the host. The buffer stores the audio data to generate a first audio packet and determines relationships between a data volume of the first audio packet and a first upper threshold and a first lower threshold. The second interface outputs the first audio packet and a clock signal to a codec apparatus. In response to the data volume of the first audio packet being less than the first lower threshold, the buffer outputs an underflow interrupt signal. In response to the data volume of the first audio packet being greater than the first upper threshold, the buffer outputs an overflow interrupt signal.

A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.

According to an embodiment, a signal generation circuit includes a generation unit configured to generate a second clock signal from division of a first clock signal and generate a timing signal with a cycle length that is a sum of a predetermined number of half-cycle periods of the second clock signal. A period changing unit of the signal generation circuit is configured to adjust the cycle length of the timing signal by changing a length of at least one half-cycle period of the second clock signal. An output unit of the signal generation circuit is configured to output the second clock signal and the timing signal.

According to an embodiment, a signal generation circuit includes a generation unit configured to generate a second clock signal from division of a first clock signal and generate a timing signal with a cycle length that is a sum of a predetermined number of half-cycle periods of the second clock signal. A period changing unit of the signal generation circuit is configured to adjust the cycle length of the timing signal by changing a length of at least one half-cycle period of the second clock signal. An output unit of the signal generation circuit is configured to output the second clock signal and the timing signal.

A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.

A variable capacitance circuit may operate a Metal Oxide Semiconductor (MOS) transistor or other semiconductor device to switch a capacitor in and out. Several circuits may be combined in a parallel network having offset bias voltages, such that the combined network may produce a variable capacitance over a large voltage range. The variable capacitance circuit may be incorporated into a phase locked loop (PLL) circuit where similar devices may be configured to produce a voltage reference as part of the PLL circuitry. Such a circuit may be immune to temperature, process, or voltage variances, since the current pulse magnitude times the low pass filter resistance times the sensitivity of a controlled voltage oscillator can be held constant.

A variable capacitance circuit may operate a Metal Oxide Semiconductor (MOS) transistor or other semiconductor device to switch a capacitor in and out. Several circuits may be combined in a parallel network having offset bias voltages, such that the combined network may produce a variable capacitance over a large voltage range. The variable capacitance circuit may be incorporated into a phase locked loop (PLL) circuit where similar devices may be configured to produce a voltage reference as part of the PLL circuitry. Such a circuit may be immune to temperature, process, or voltage variances, since the current pulse magnitude times the low pass filter resistance times the sensitivity of a controlled voltage oscillator can be held constant.

The present invention discloses a clock data recovery method having quick locking and bandwidth stabilizing mechanism used in a clock data recovery circuit. A relative position relation between a serial data and a sampling clock is detected by a phase detection circuit in an adaptive control period to generate a tracking direction. The tracking direction of a first clock period is directly outputted as an adaptive tracking direction by an adaptive tracking circuit. For each of the clock periods behind the first clock period, a previous tracking direction is replaced by a current tracking direction only when the current tracking direction exists and is different from the previous tracking direction of a previous clock period such that an actual tracking direction is generated when the adaptive tracking direction changes. The phase of the sampling clock is adjusted according to the actual tracking direction by a clock control circuit.