An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.

A converter system includes a rectifier, a DC link stage and an inverter connected in series. A control unit includes a slow reference frame angle determination unit that generates a slow reference frame angle θ.sub.r,slow representing an angle that is slowly following a grid phase deviation, and a fast Phase Locked Loop generating a fast reference frame angle θ.sub.r,fast representing an angle that is fast following a grid phase deviation. The control unit uses the slow reference frame angle θ.sub.r,slow and the fast reference frame angle θ.sub.r,fast to control the rectifier output current, and the fast reference frame angle θ.sub.r,fast to control the inverter output voltage and to synchronize the inverter output voltage with the grid voltage.

A converter system includes a rectifier, a DC link stage and an inverter connected in series. A control unit includes a slow reference frame angle determination unit that generates a slow reference frame angle θ.sub.r,slow representing an angle that is slowly following a grid phase deviation, and a fast Phase Locked Loop generating a fast reference frame angle θ.sub.r,fast representing an angle that is fast following a grid phase deviation. The control unit uses the slow reference frame angle θ.sub.r,slow and the fast reference frame angle θ.sub.r,fast to control the rectifier output current, and the fast reference frame angle θ.sub.r,fast to control the inverter output voltage and to synchronize the inverter output voltage with the grid voltage.

A semiconductor die is provided. The semiconductor die includes a D2D transceiver composed of a single die or dual dies. The D2D transceiver includes a first D2D transmitter and a first D2D receiver. The D2D transmitter is configured to send data to a second D2D receiver in a second D2D transceiver of another semiconductor die using a first reference clock signal. The D2D receiver is configured to receive data from a second D2D transmitter in the second D2D transceiver using a second reference clock signal. Through using the embodiments of the disclosure, a transmission solution may be flexibly configured for a multi-application scenario including D2D.

A semiconductor die is provided. The semiconductor die includes a D2D transceiver composed of a single die or dual dies. The D2D transceiver includes a first D2D transmitter and a first D2D receiver. The D2D transmitter is configured to send data to a second D2D receiver in a second D2D transceiver of another semiconductor die using a first reference clock signal. The D2D receiver is configured to receive data from a second D2D transmitter in the second D2D transceiver using a second reference clock signal. Through using the embodiments of the disclosure, a transmission solution may be flexibly configured for a multi-application scenario including D2D.

A clock and data recovery circuit includes a voltage controlled oscillator, a frequency detector and a control circuit. The voltage controlled oscillator is configured to generate a clock signal according to a voltage signal. The frequency detector is configured to detect whether increasing a frequency of the clock signal is required according to a plurality of sampling results of the input data signal and accordingly generate a first up control signal. The control circuit is coupled to the voltage controlled oscillator and the frequency detector and configured to adjust the voltage signal according to the first up control signal. The clock and data recovery circuit operates in a data recovery mode after detecting that the frequency of the clock signal is locked, and the frequency detector is configured to detect whether increasing the frequency of the clock signal is required in the data recovery mode.

A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.

In one embodiment, the voltage droop monitoring circuit includes a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals based on a first control signal. The first control signal is based on a power supply voltage of a functional circuit block. The voltage droop monitoring circuit further includes a counter configured to generate a count value based on the selected oscillation signal, and a droop detector configured detect droop in the power supply voltage of the functional circuit block based on the count value and at least one threshold value.

In one embodiment, the voltage droop monitoring circuit includes a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals based on a first control signal. The first control signal is based on a power supply voltage of a functional circuit block. The voltage droop monitoring circuit further includes a counter configured to generate a count value based on the selected oscillation signal, and a droop detector configured detect droop in the power supply voltage of the functional circuit block based on the count value and at least one threshold value.

A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.