A phase locked loop circuit that is capable of stabilizing a frequency of an input signal even in the case where the frequency is unstable is provided. The phase locked loop circuit 12 that corrects a frequency error of an output signal from an oscillator to a predetermined target frequency; an ADC 121 that converts the output signal to a digital signal; reference frequency output means 123 that outputs a reference frequency signal; frequency error detection means 122a that detects the frequency error based on the digital signal and the reference frequency signal; correction signal generation means 122b that generates an error correction signal based on the frequency error; a DAC 124 that converts the error correction signal to an analog signal; and a multiplier 125 that multiplies the output signal by the analog signal to correct the frequency error of the output signal.

An example pulse generation circuit includes a parallel-to-serial circuit configured to convert parallel data to serial data according to parallel clock signal and a serial clock signal, the serial data comprises a sequence of pulses; a clock generator configured to generate a clock signal; and a phase controller configured to generate the serial clock signal from the clock signal based on a phase control signal.

Methods and digital circuits providing frequency correction to frequency synthesizers are disclosed. An FLL digital circuit is provided that is configured to handle a reference frequency that is dynamic and ranges over a multi-decade range of frequencies. The FLL circuit includes a digital frequency iteration engine that allows for detection of disappearance of a reference frequency. When the digital frequency iteration engine detects that the reference frequency signal is not available, the oscillator generated frequency is not corrected, and the last value of the oscillator generated frequency is held until the reference frequency signal becomes available again. This FLL circuit is also preceded by a low-pass filter which is dynamically tuned to the frequency to which the FLL locks, eliminating harmonic components in the original signal which might otherwise cause errors in frequency estimation.

Methods and digital circuits providing frequency correction to frequency synthesizers are disclosed. An FLL digital circuit is provided that is configured to handle a reference frequency that is dynamic and ranges over a multi-decade range of frequencies. The FLL circuit includes a digital frequency iteration engine that allows for detection of disappearance of a reference frequency. When the digital frequency iteration engine detects that the reference frequency signal is not available, the oscillator generated frequency is not corrected, and the last value of the oscillator generated frequency is held until the reference frequency signal becomes available again. This FLL circuit is also preceded by a low-pass filter which is dynamically tuned to the frequency to which the FLL locks, eliminating harmonic components in the original signal which might otherwise cause errors in frequency estimation.

An oscillator circuit includes an oscillating unit, a counter unit, and a set value generator. The oscillating unit is configured to output an oscillation signal having a frequency corresponding to an input frequency setting value. The counter unit is configured to count a number of pulses of the oscillation signal during a time period corresponding to a period of a reference signal input from outside. The set value generator is configured to generate the frequency setting value every predetermined time period based on the count of the pulses counted by the counter unit.

Methods, systems, and devices for wireless communication are described. An internal state of a frequency divider of a local oscillator (LO) may be stored using a storage device in order to facilitate phase flipping of one or more signals output by the LO. The frequency divider may also include a pulse swallower that swallows a pulse of a signal input into the frequency divider. Using one or more power supply cutting switches in combination with a storage device and pulse swallower, high speed and reliable phase flipping of LO signals may be performed.

A transmitting device for wireless transmission of measured parameters comprising a microcontroller and pulse generating elements connected to the microcontroller, the microcontroller being configured to receive at least one detection signal representative of at least one measured parameter value and being also configured to control the pulse generating elements so that the pulse generating elements generate at least one pulse position modulation (PPM) signal comprising information corresponding to the at least one measured parameter value, the transmitting device further comprising or being connectable to an antenna for the wireless transmission of the PPM signal, the pulse generating elements comprising an oscillator and a power amplifier connected to the oscillator in order to amplify the pulses output from the oscillator and to output the PPM signal.

A transmitting device for wireless transmission of measured parameters comprising a microcontroller and pulse generating elements connected to the microcontroller, the microcontroller being configured to receive at least one detection signal representative of at least one measured parameter value and being also configured to control the pulse generating elements so that the pulse generating elements generate at least one pulse position modulation (PPM) signal comprising information corresponding to the at least one measured parameter value, the transmitting device further comprising or being connectable to an antenna for the wireless transmission of the PPM signal, the pulse generating elements comprising an oscillator and a power amplifier connected to the oscillator in order to amplify the pulses output from the oscillator and to output the PPM signal.

A synchronization circuit may include: a delay line configured to delay a reference clock signal; a division circuit configured to generate a divided feedback clock signal by dividing a feedback clock signal at a division ratio which is set according to a division ratio control signal; a phase detection circuit configured to generate a phase detection signal by detecting the phase of the divided feedback clock signal based on the reference clock signal; and a delay line control circuit configured to control a delay time of the delay line according to the phase detection signal and the divided feedback clock signal.

An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.