A clock frequency divider circuit and a receiver are provided. The clock frequency divider circuit includes a reset retimer circuit configured to receive a reset signal and a clock signal, output a reset buffer signal of a differential signal pair obtained by buffering the reset signal, and output a reset synchronization signal obtained by synchronizing the reset signal with the clock signal, a clock buffer circuit configured to receive the clock signal and the reset synchronization signal and output a clock buffer signal of a differential signal pair obtained by buffering the clock signal, and an IQ divider circuit configured to output first through fourth output signals having different phases based on the reset buffer signal and the clock buffer signal.

Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

A clock integrated circuit is provided. The clock integrated circuit includes: a first clock generator which includes a crystal oscillator configured to generate a first clock signal; and a second clock generator which includes a resistance-capacitance (RC) oscillator and a first frequency divider, and is configured to: generate a second clock signal using the first frequency divider based on a clock signal output from the RC oscillator; perform a first calibration operation for adjusting a frequency division ratio of the first frequency divider to a first frequency division ratio based on the first clock signal; and perform a second calibration operation for adjusting the first frequency division ratio to a second frequency division ratio based on a sensed temperature.

Frequency synthesizers having reduced phase noise and a small step size. One example can provide frequency synthesizers having low phase noise by eliminating dividers in a feedback path and instead employing frequency converters, such as mixers. Step size can be further reduced by providing frequency converters in a reference signal feedforward path. Acquisition time can be decreased by employing a fast-acquisition phase-locked loop that is switched out after acquisition in favor of a low phase-noise phase-locked loop. Another example can reduce phase noise by employing a YIG oscillator. To improve acquisition time, a first, faster phase-locked loop can be used to lock to a signal before switching to a second, slower phase-locked loop that includes the YIG oscillator. Another example can provide low noise by including phase-locked loops that operate in a frequency range having low thermal noise while a frequency of an output signal varies over a wide range.

The data recovery from gradients (DRG) of sub-carriers of a received OFDM signal affected by deterministic and random distortions introduced by a transmission link, contributes a method and a system for utilizing gradients characterizing shapes of OFDM sub-carriers comprised in such OFDM signal for recovering data symbols transmitted originally.

The data recovery from gradients (DRG) of sub-carriers of a received OFDM signal affected by deterministic and random distortions introduced by a transmission link, contributes a method and a system for utilizing gradients characterizing shapes of OFDM sub-carriers comprised in such OFDM signal for recovering data symbols transmitted originally.

A device for OOK modulating an input signal, comprising at least: an injection-locked oscillator comprising a power supply input, an injection signal input and an output to which the OOK modulated signal is to be delivered; a first controlled switch comprising a control input to which the input signal is to be applied, and configured to couple or not a power supply source to the power supply input of the injection-locked oscillator in dependence on the value of the input signal; a periodic signal providing device configured to deliver, on an output which is electrically coupled to the injection signal input of the injection-locked oscillator, a periodic injection signal whose frequency and amplitude trigger locking of the injection-locked oscillator at the frequency of the injection signal or a multiple of this frequency.

A device for OOK modulating an input signal, comprising at least: an injection-locked oscillator comprising a power supply input, an injection signal input and an output to which the OOK modulated signal is to be delivered; a first controlled switch comprising a control input to which the input signal is to be applied, and configured to couple or not a power supply source to the power supply input of the injection-locked oscillator in dependence on the value of the input signal; a periodic signal providing device configured to deliver, on an output which is electrically coupled to the injection signal input of the injection-locked oscillator, a periodic injection signal whose frequency and amplitude trigger locking of the injection-locked oscillator at the frequency of the injection signal or a multiple of this frequency.

A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.

A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.