A multi-stage analog-to-digital converter (ADC) suitable for low power applications, such as glucose monitoring, may be required to digitize a slow-moving signal. As such, a multi-stage ADC must be versatile. Accordingly, the multi-stage ADC can be configured to operate at different bandwidths and resolutions through the use of ADC stages that can be enabled or disabled in an exchange between resolution and speed. Each ADC stage digitizes an input signal (e.g., a voltage or a current) using an analog comparison to access a lookup table for a digital signal that represents the input signal at a particular accuracy. Unlike other multi-stage approaches, the digitization is asynchronous (i.e., requires no clock) and can provide simplicity, speed, and low-power operation to the multi-stage ADC.

To provide a display device having a small circuit area and low power consumption. The display device includes a semiconductor device and a D/A converter circuit, and the semiconductor device includes first to third transistors and first and second capacitors. A first terminal of the first transistor is electrically connected to a first terminal of the first capacitor. A first terminal of the second transistor is electrically connected to a gate of the third transistor, a second terminal of the first capacitor, and a first terminal of the second capacitor. A first terminal of the third transistor is electrically connected to a second terminal of the second capacitor. An output terminal of the D/A converter circuit is electrically connected to a second terminal of the first transistor and a second terminal of the second transistor. Supply of a potential to the first terminal of the first capacitor changes(finely adjusts) the potential of the gate of the third transistor to be more precise than a potential that can be output from the D/A converter circuit.

A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

A circuit includes a first external terminal, a first lower resolution analog-to-digital converter (LRADC) coupled to the external terminal and configured to perform a first conversion of an analog signal received at the external terminal to a digital value, and a higher resolution analog-to-digital converter (HRADC). The HRADC is configured to selectively receive the analog signal from the first external terminal based on the digital value. When the digital value outputted by the first LRADC indicates a change in value of the received analog signal, the HRADC is provided with the analog signal and performs a second conversion of the analog signal to a second digital value. The first LRADC has a lower conversion resolution as compared to the HRADC.

A terminal may obtain a parameter related to energy consumption of the terminal, determine a bit resolution value of an analog-to-digital converter (ADC) of the terminal for reducing the energy consumption of the terminal, and set the bit resolution value of the ADC as the determined bit resolution value.

Aspects of the subject disclosure may include, for example, a process that encodes a number of digital signals representing image data captured by a video camera, the image data being provided by the video camera in accordance with a 4K ultra-high definition (4K-UHD) standard. The number of digital signals are provided to a multiplexing unit that outputs a multiplexed signal including a number of optical wavelengths, the multiplexed signal being transmitted on a single fiber-optic cable unidirectionally from the multiplexing unit to a presentation device. The multiplexed signal is transmitted on the single cable unidirectionally from the proximal end to the distal end. Other embodiments are disclosed.

An analog to digital converting circuit includes a correlated double sampling circuit (CDS) that compares a pixel signal with a ramp signal, and outputs a comparison signal, a timing amplifier that increases an active time of the comparison signal N times, and outputs an extended signal, wherein the N is a positive integer, and a counter that outputs a digital signal corresponding to the pixel signal in response to the extended signal and a first clock signal.

A counter, a counting method and an apparatus for image sensing are introduced in the present disclosure. The counter includes a plurality of dual phase clock generators and a plurality of column counters. Each of the plurality of dual phase clock generator receives a common clock signal and generates dual phase clock signals which comprise a first clock signal and a second clock signal according to the common clock signal. Each of the plurality of column counters is coupled to one of the plurality of dual phase clock generators to receive the first clock signal and the second clock signal, and is configured to output a counting value according to the first clock signal and the second clock signal. Each of the plurality of dual phase clock generators provides the first clock signal and the second clock signal to a group of the plurality of column counters.

An analog to digital converting circuit includes a correlated double sampling circuit (CDS) that compares a pixel signal with a ramp signal, and outputs a comparison signal, a timing amplifier that increases an active time of the comparison signal N times, and outputs an extended signal, wherein the N is a positive integer, and a counter that outputs a digital signal corresponding to the pixel signal in response to the extended signal and a first clock signal.

Aspects of the subject disclosure may include, for example, a device that encodes digital signals representing image data captured by a video camera and provided according to a 4K ultra-high definition (4K-UHD) standard. The digital signals are transmitted as serial digital interface (SDI) streams to a wavelength-division multiplexing (WDM) unit; the WDM unit performs electrical-to-optical conversion of the SDI streams and outputs a multiplexed signal to a single fiber-optic cable. The video camera, encoding unit, and WDM unit form a combined module within a housing; the device connects to a proximal end of a single fiber-optic cable, and a distal end of the single fiber-optic cable is configurable for connection to a demultiplexer of a 4K-UHD video presentation device. The multiplexed signal is transmitted on the single fiber-optic cable unidirectionally from the proximal end to the distal end. Other embodiments are disclosed.