A method of expanding current steering Digital-to-Analog Converter (DAC) output amplitude and enhancing linearity performance. Level shifters with regulated supply and ground voltage are inserted before current source latches. Extra devices and small current are placed between switches and resistor load to enhance the linearity of current steering DAC.

Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example device for digital-to-analog conversion generally includes: a digital-to-analog converter (DAC) having an input coupled to an input node of the device; a first return-to-zero (RZ) DAC having an input coupled to an input node of the device; and a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the first RZ DAC is coupled to a second input of the combiner.

A method of expanding current steering Digital-to-Analog Converter (DAC) output amplitude and enhancing linearity performance. Level shifters with regulated supply and ground voltage are inserted before current source latches. Extra devices and small current are placed between switches and resistor load to enhance the linearity of current steering DAC.

An analog-to-digital converter (ADC) system, such as a subranging ADC, including a cascade of buffer circuits and signal processing circuitry to measure and cancel the distortion introduced by the buffer circuits. Thus, buffer circuits can be added to the signal path of an input signal without the detrimental effects, such as added distortion, that typically accompany the addition of buffers.

Technologies are provided for adaptive control of bias settings in a digital microphone. In some embodiments, a device includes a first component that provides data indicative of a clock frequency of operation in a functional mode of a digital microphone. The clock frequency clocks one or more microphone components having switching activity. The device also can include a second component that determines, using the clock frequency, an amount of bias current to supply to at least a first microphone component of the one or more microphone components. The device can further include a memory device that retains control parameters that include at least one of a first subset of parameters defining a relationship between current and frequency and a second subset of parameters defining a quantization of the relationship. The quantization including multiple bias current levels for respective frequency intervals.

Example embodiments relate to systems and methods for analog-to-digital signal conversion. One embodiment includes a system for analog-to-digital signal conversion. The system includes an analog input signal. The system also includes a digital-to-analog converter configured to generate a reference signal. Further, the system includes an amplifier configured to amplify an error signal that includes a difference between the analog input signal and the reference signal. Additionally, the system includes a level-crossing based sampling circuit that includes a first comparator configured to compare the error signal with respect to a first reference level, and a second comparator configured to compare the error signal with respect to a second reference level, thereby generating event-based reset signals corresponding to a plurality of sampling instances in order to reset the digital-to-analog converter. Yet further, the system includes a trigger circuit configured to generate reset signals asynchronous to the event-based reset signals.

A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.

Certain aspects of the present disclosure are directed to a radio frequency digital-to-analog converter (RFDAC). The RFDAC generally includes a plurality of digital-to-analog (DAC) unit cells. At least one DAC unit cell is capable of being configured in an active state or in a sleep state. For the at least one DAC unit cell, an output impedance of the DAC unit cell in the active state is equal to an output impedance of the DAC unit cell in the sleep state.

Technologies are provided for adaptive control of bias settings in a digital microphone. In some embodiments, a device includes a first component that provides data indicative of a clock frequency of operation in a functional mode of a digital microphone. The clock frequency clocks one or more microphone components having switching activity. The device also can include a second component that determines, using the clock frequency, an amount of bias current to supply to at least a first microphone component of the one or more microphone components. The device can further include a memory device that retains control parameters that include at least one of a first subset of parameters defining a relationship between current and frequency and a second subset of parameters defining a quantization of the relationship. The quantization including multiple bias current levels for respective frequency intervals.

A method and an apparatus for determining and compensating respective harmonic distortions of digital to analog and analog to digital conversions are described. A signal from a digital to analog converter is passed through a plurality of calibration paths. Output signals from each calibration path, converted by an analog to digital converter, are analyzed in order to determine the harmonic distortions introduced by each side of the chain separately. One embodiment represents a digital sine generator which has harmonic distortions of its analog output continually compensated. Another embodiment compensates harmonic distortions introduced by an analog to digital converter in order to measure harmonic distortions of an analog signal precisely. Other embodiments are described and shown.