Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.

A method comprises at least the following steps: generating pseudo random noise in the digital domain coded on a number N of bits, sampled at a given frequency FH/N; multiplexing in the digital domain the binary signals produced by each of the N bits at a sampling frequency FH so as to obtain noise coded on one bit at said frequency FH; transferring the noise thus coded into the analog domain via a low-voltage differential transmission interface; filtering the analog signal in a passband which can be centered on half the sampling frequency of an analog-digital converter.

A SAR ADC (50) is disclosed. It comprises a differential input port having a first input (V.sub.inP) configured to receive a first input voltage and a second input (V.sub.inN) configured to receive a second input voltage, of opposite polarity compared with first input voltage. Furthermore, it comprises a (300) having a first sub circuit (310P) comprising a first plurality of capacitors (2C.sub.u, C.sub.u), each connected to a common node (320P) of the first sub circuit (310P) with a first terminal, and a second sub circuit (310N) comprising a second plurality of capacitors (2C.sub.u, C.sub.u), each connected to a common node (320N) of the second sub circuit (310N) with a first terminal. For each capacitor (2C.sub.u, C.sub.u) of the first plurality of capacitors, the first sub circuit (310P) comprises a first switch (S4) connected between the first input (V.sub.inP) of the SAR ADC and a second terminal of that capacitor, a second switch (S.sub.2) connected between a first reference-voltage input (V.sub.rP) and the second terminal of that capacitor, a third switch (S.sub.1) connected between a second reference-voltage input (V.sub.rN) and the second terminal of that capacitor, and a capacitive device (X.sub.P) connected between the second input (V.sub.inN) of the SAR ADC and the second terminal of that capacitor. The second sub circuit is arranged in a similar way.

An interleaved Analog-to-Digital Converter (ADC) has a reference channel receiving an attenuated analog input. The reference channel is also calibrated to remove capacitor-ratio mismatch, static, and dynamic mismatches and produces a linear replica of the data channels with negligible nonlinear errors due to attenuation. Nonlinear errors on the data channels are corrected by Harmonic Distortion HD2 and HD3 coefficients. A counter increments when the sign bit of a nonlinear-corrected channel code is negative. The count is doubled and reduced by a number of samples to generate a HD2 cost function that adjusts the HD2 coefficient in a LMS loop. A HD3 correlation is generated by multiplying the reference channel output by its difference with the nonlinear-corrected channel code. The sign of the correlation code increments a second counter which generates a HD3 cost function whose sign bit adjusts the HD3 coefficient. These 2 counters generate cost functions, eliminating sample storage.

An apparatus configured to transmit and receive a radio frequency (RF) signal is provided. The apparatus includes a digital-to-analog converter (DAC) configured to convert a digital signal into an analog signal, a power amplifier configured to amplify the analog signal, and an antenna configured to output, as the RF signal, the amplified analog signal to the outside. The DAC includes a current cell matrix including a plurality of current cells configured to generate the analog signal, a plurality of normal paths configured to control the plurality of current cells to be turned on or off, based on the digital signal, and a plurality of alternative paths configured to selectively consume power, based on a pattern of the digital signal.

A system and method for equalization of a linear or non-linear system. The system includes an adder configured to add an analog reference signal and an input signal, a processing system configured to process a sum of the analog reference signal and the input signal, a non-linear equalizer (NLEQ) configured to process an output of the processing system to remove a distortion incurred by the processing system, a calibration circuitry configured to generate a reconstructed reference signal in digital domain based on measurement of the analog reference signal, and generate coefficients for the NLEQ based on the reconstructed reference signal and the output of the processing system, and a subtractor configured to subtract the reconstructed reference signal from an output of the NLEQ. The analog reference signal may be a sinusoid including single or multiple tones of sinusoids. The non-linear system may be an analog-to-digital converter (ADC).

A amplifier system may include a predistorter receiving an input signal to generate a predistortion signal, a first converter receiving the predistortion signal to generate a preamplified signal, a power amplifier receiving the preamplified signal to generate an output signal based on the preamplified signal and the input signal, and a second converter sampling the output signal to generate a feedback signal. The power amplifier may produce a distortion signal at a first frequency, the second converter may sample the output signal using a timing signal with a second frequency that is lower than the first frequency to generate the feedback signal, and the predistorter, based upon the feedback signal, may predistort the predistortion signal to reduce the distortion signal at the first frequency.

An interleaved Analog-to-Digital Converter (ADC) has a reference channel receiving an attenuated analog input. The reference channel is also calibrated to remove capacitor-ratio mismatch, static, and dynamic mismatches and produces a linear replica of the data channels with negligible nonlinear errors due to attenuation. Nonlinear errors on the data channels are corrected by Harmonic Distortion HD2 and HD3 coefficients. A counter increments when the sign bit of a nonlinear-corrected channel code is negative. The count is doubled and reduced by a number of samples to generate a HD2 cost function that adjusts the HD2 coefficient in a LMS loop. A HD3 correlation is generated by multiplying the reference channel output by its difference with the nonlinear-corrected channel code. The sign of the correlation code increments a second counter which generates a HD3 cost function whose sign bit adjusts the HD3 coefficient. These 2 counters generate cost functions, eliminating sample storage.

A device can be used for compensating bandwidth mismatches of time interleaved analog to digital converters. A processor of the device determines, for each original sample stream, an estimated difference between the time constant of a low pass filter representative of the corresponding converter and a reference time constant of a reference low pass filter, and uses this estimated difference and a filtered stream to correct the original stream and deliver a corrected stream of corrected samples.

A hybrid analog-digital electronic circuit for solving non-linear programming problems includes an analog circuit and a digital microcontroller interconnected to each other by an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). The analog circuit physically realizes a nonlinear programming problem (NLP) where voltages in the analog circuit represent variables in the NLP, and the interconnection of the analog circuit components enforce Karush-Kuhn-Tucker (KKT) conditions on the variables, such that the voltages in the analog circuit that represent the variables of the NLP naturally converge to an optimal and feasible solution of the NLP. The digital microcontroller sets the voltages in the analog circuit at particular nodes in the analog circuit through the DAC, where the voltages set at the particular nodes determine a precise cost function to be minimized by the analog circuit, where the voltages set at the particular nodes are computed by the digital microcontroller based on measurements obtained from the analog circuit through the ADC.