Various techniques that can provide a capability to background calibrate ADC linearity error, e.g., due to capacitor mismatch drift and other parameter drift, during normal ADC operation in which analog-to-digital signal conversions are ongoing. A method can include grouping capacitors of an ADC into multiple clusters and calibrating under an arbitrary signal condition. To quickly converge the calibration result, the same arbitrary signal can be converted twice, and the capacitor(s) being calibrated can be modulated after first conversion. The difference between the results of the first and second conversions can contain the error information that can be used for calibration, and the signal component can be removed by this process. These techniques can provide improved linearity at 20-bit level and beyond.

An analog-to-digital converter (ADC) and method of operation thereof are provided for converting an analog signal to a digital signal. The ADC utilizes Correlated Electron Material (CEM) devices that may contain a transition metal oxide (TMO), such as Nickel Oxide (NiO). The ADC may include an interconnect circuit that is operable to couple a power supply to the CEM devices. The power supply is controlled to program the resistance of the CEM devices and thereby control performance characteristics of the ADC.

The overall performance of a dual-path ADC system may be improved by using a VCO-based ADC for small-amplitude signals and employing non-linear cancelation to remove nonlinearities in signals output by the VCO-based ADC. In particular, VCO-based dual-path ADC systems of this disclosure may be configured to receive a first digital signal from a first ADC and a second digital signal from a second ADC, wherein the second digital signal is more non-linear than the first digital signal. The dual-path systems may also be configured to determine one or more non-linear coefficients of the second digital signal based, at least in part, on processing of the first and second digital signals. The dual-path systems may be further configured to modify the second digital signal based, at least in part, on the determined one or more non-linear coefficients to generate a more linear second digital signal.

A flash analog-to-digital converter (ADC) includes comparators that convert an analog input signal to a digital output signal. Offsets of these comparators introduce noise and can hurt the performance of the ADC. Thus, these comparators are calibrated using calibration codes. Conventional calibration methods determine these calibration codes by removing the ADC from an input signal. Otherwise, it is difficult to distinguish the noise from the signal in the calibration measurement. In contrast, an embodiment can determine the calibration codes while the ADC converts the input signal to a digital signal. Such an embodiment can be achieved by a frequency-domain technique. In an embodiment employing a frequency-domain power meter, an input signal can be removed from the power measurement. This removal enables accurate measurement of in-band noise without having the measurement be corrupted by input signal power.

A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers. Then each of the other samplers of the ADC, one at a time, is calibrated by selecting an uncalibrated sampler and establishing it as the current Sampler Under Calibration (SUC); disregarding contribution of the SUC to the output of the ADC; adjusting the threshold of the SUC to be identical to the threshold of the reference sampler; performing one-bit cross-correlation between the reference sampler and the SUC; establishing an error surface representing the threshold offset and timing offset of the SUC with respect to the reference sampler; adjusting the threshold and the timing of the SUC to be equal to the threshold and timing of the reference sampler; restoring level of the SUC to its original threshold with respect to the overall ADC and restoring contribution of the SUC to the output of the ADC.

An analog signal input circuit with a first number of analog signal detection channels and a diagnostics circuit, with each analog signal detection channel including a third number of analog signal detection circuits and a first connection selection device, and each analog signal detection circuit comprising a first connection device and a second connection device. For each analog signal detection channel, for detecting analog input signals applied at analog signal inputs from a second number of analog signal inputs, and for the respective issuance of output signals for the detected analog input signals, respectively one analog signal detection circuit is alternatingly selected for a certain period of time, not connected to its first connection device comprising an analog signal input for detecting an analog input signal, but used for testing and/or diagnostic purposes.

The present invention relates to a method and apparatus for providing digital background calibration for mismatches in M-channel time-interleaved ADCs(TI-ADCs), more specifically providing a pure digital blind calibration technique for offset mismatch, gain mismatch and time mismatch, which are essentially incurred by utilizing a time-interleaved analog-digital converter in systems having to process data with high speeds. Wherein the offset mismatch and gain mismatch are corrected based on statistical characteristics of the digital signals which are sampled and outputted in channel by channel, and the time mismatch is corrected based on a derivative filter and a delay filter. Thereby the present invention relating to a method and apparatus for digital background calibration enables the hardware complexity to be reduced and the efficiency of hardware resource to be increased. The pure digital background calibration of mismatches base on addition, subtraction and multiplication operations is also independent of foundaries and processes, and significantly reduces the design complexity.

The embodiments described herein provide analog-to-digital converters (ADCs) and systems and methods for calibrating ADCs, including ADCs with poorly characterized nonlinearities that cannot be effectively calibrated with traditional calibration techniques. In general, the embodiments described herein calibrate by measuring output values from an ADC with a known calibration input values being applied. The measured output values are used to determine localized polynomial interpolants. Each of the determined localized polynomial interpolants is then evaluated at an uncorrected output value, and the evaluated localized polynomial interpolants are then used to generate correction values. These correction values can then be used to calibrate the ADC during later operation. Such a calibration technique can provide effective calibration for a variety of ADCs, including ADCs that use inverter-based voltage-to-current (VI) converters and current-controlled ring oscillators.

A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers. Then each of the other samplers of the ADC, one at a time, is calibrated by selecting an uncalibrated sampler and establishing it as the current Sampler Under Calibration (SUC); disregarding contribution of the SUC to the output of the ADC; adjusting the threshold of the SUC to be identical to the threshold of the reference sampler; performing one-bit cross-correlation between the reference sampler and the SUC; establishing an error surface representing the threshold offset and timing offset of the SUC with respect to the reference sampler; adjusting the threshold and the timing of the SUC to be equal to the threshold and timing of the reference sampler; restoring level of the SUC to its original threshold with respect to the overall ADC and restoring contribution of the SUC to the output of the ADC.

Described is an apparatus which comprises: a digital-to-analog converter (DAC) having a DAC cell with p-type and n-type current sources and an adjustable strength current source which is operable to correct non-linearity of the DAC cell caused by both the p-type and n-type current sources; and measurement logic, coupled to the DAC, having a reference DAC cell with p-type and n-type current sources, wherein the measurement logic is to monitor an integrated error contributed by both the p-type and n-type current sources of the DAC cell, and wherein the measurement logic is to adjust the strength of the adjustable strength current source according to the integrated error and currents of the p-type and n-type current sources of the reference DAC cell.