Techniques that enable calibration of digital-to-analog Converters (DACs) with minimal processing overhead. A single frequency bin can be used to calibrate errors between bits. A low frequency feedback path can be included into a low frequency low power ADC to determine the error signal that exists in the calibration bin. The bits are calibrated when this error signal is minimized. The calibration techniques described provide an extremely efficient and optimal calibration at the DAC output of both static and dynamic errors.

A dither capacitor, separate from the capacitor sampling the input signal, can be used to inject the additive dither in the switched-capacitor network of the track and hold circuit. This implementation can be referred to as a split-capacitor dither injection. The dither capacitor can be connected to a summing node of the switched-capacitor network. Using a separate capacitor allows the dither to be isolated from the capacitor that is sampling the input signal and avoids kick-back errors.

There is provided a RF-DAC that may include (i) a first PAM that includes a first group of first power amplifiers of different amplifications, (ii) a second PAM that includes a second group of second power amplifiers of different amplifications; (iii) a load that includes an output port and a transformer; (iv) power amplifiers control units, and a transformer control unit. During a cycle of operation (i) each one of the first and second PAMs is configured to receive one or more power amplifiers digital control signals and activate a single power amplifier per each of the first and second PAMS, (ii) the transformer control unit is configured to receive a transformer digital control signal and control a transformer parameter of the transformer, and (iii) the transformer is configured to receive a first PAM output signal and a second PAM output signal, and output a transformer output signal that reflects digital information represented by the one or more power amplifiers digital control signals and the transformer digital control signal.

An instrument configured to process signal data is disclosed. The instrument is operable to control and or change the sampling rate of the signal data from a first sample rate to a second sample rate different than the first sample rate.

A successive-approximation analog-to-digital converter includes a sampling circuit for sampling an analog input signal to acquire a sampled voltage, and a regenerative comparator for comparing the sampled voltage with a succession of reference voltages to generate, for each reference voltage, a decision bit indicating the comparison result. The converter also includes a digital-to-analog converter which is adapted to generate the succession of reference voltages, in dependence on successive comparison results in the comparator, to progressively approximate the sampled voltage. The regenerative comparator comprises an integration circuit for generating output signals defining the decision bits, and a plurality of regeneration circuits for receiving these output signals. The regeneration circuits are operable, in response to respective control signals, to store respective decision bits defined by successive output signals from the integration circuit.

A pipeline analog to digital converter (ADC) includes converter circuitries, a detector circuitry, and a clock generator circuit. The converter circuitries sequentially convert an input signal to be digital codes. One of the converter circuitries includes a sub-ADC circuit and a multiplying digital to analog converter (MDAC) circuit. The sub-ADC circuit performs a quantization according to a first signal to generate a corresponding one of the digital codes, in which the first signal is the input signal or a previous stage residue signal. The MDAC circuit processes the corresponding one of the digital codes in response to a first clock signal, in order to generate a current stage residue signal. The detector circuitry detects whether the quantization is complete, in order to generate a control signal. The clock generator circuit adjusts a timing of the first clock signal according to the control signal.

A pipeline analog to digital converter includes converter circuitries and a calibration circuitry. The converter circuitries sequentially convert an input signal into first digital codes. A first converter circuitry in the converter circuitries performs a quantization according to a first signal to generate a first corresponding digital code in the first digital codes, and the first signal is a signal, which is processed by the first converter circuitry, of the input signal and a previous stage residue signal. The calibration circuitry combines the first digital codes to output a second digital code, detects whether the quantization is completed to generate first and second valid signals, and determines whether to set the second digital code to be a first predetermined digital code or a second predetermined digital code according to the first and the second valid signals. The second valid signal is a delay signal of the first valid signal.

An analog-to-digital converter (ADC) system includes a main ADC, a reference ADC, a sampling control circuit, and a calibration circuit. The main ADC obtains a first sampled input voltage by sampling an analog input according to a first sampling clock, and performs analog-to-digital conversion upon the first sampled voltage to generate a first sample value. The reference ADC obtains a second sampled voltage by sampling the analog input according to a second sampling clock, and performs analog-to-digital conversion upon the second sampled voltage to generate a second sample value. The sampling control circuit controls the second sampling clock to ensure that the second sampling clock and the first sampling clock have a same frequency but different phases, and adjusts the second sample value to generate a reference sample value. The calibration circuit applies calibration to the main ADC according to the first sample value and the reference sample value.

An interleaved analog-to-digital conversion (ADC) system may have timing errors in a time domain that is corrected using phase compensation in a phase domain. The ADC system may include sub-ADCs, each receiving a clock signal, which is associated with a representation of a timing skew value, reflecting an undesired timing error. A mixer may have sub-mixers, each receiving a sub-ADC output signal and a compensated numerically controlled oscillator (NCO) value. A combiner may combine the sub-mixer output signals. A decimator may decimate the output of the combiner. Each timing skew value is in a time domain. A compensated NCO value is determined using a respective phase skew value. Each phase skew value is an offset value in phase and is not a value in time. Each phase skew value in a phase domain compensates the respective timing skew value in a time domain. Multiple ADC systems and methods are described.

Methods and devices are provided for circuits. One device includes an adjustment circuit having an adjustable resistor for modifying a resistance value of a resistive device, the adjustment circuit connected to an adjustment terminal of the resistive device. The resistance value of the adjustable resistor changes, when a voltage or charge on the adjustment terminal of the adjustable resistor is changed. The adjustable resistor is a phase change element with an adjusting terminal to which different voltage values are applied for adjusting a conversion device threshold value.