An audio distribution system and method is described herein that optimizes audio equalization settings based on a specific make and model of loudspeaker being used in an audio distribution system. The system and method comprises: generating a loudspeaker test signal; transmitting the loudspeaker test signal to a loudspeaker unit under test (LUUT); receiving an acoustic signal from the LUUT by a microphone located at a test location, the microphone generating an electrical loudspeaker test signal response (loudspeaker test signal response); converting the loudspeaker test signal response to a digitized loudspeaker test signal response; generating a spectral plot of the digitized loudspeaker test signal response for the LUUT; comparing the spectral plot of the LUUT to spectral plots of known loudspeakers, and matching the spectral plot of the LUUT to a spectral plot of a first make and model of a known loudspeaker; and obtaining a set of equalizer settings for the first make and model of the known loudspeaker.

Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter.

A digital to analog conversion, DAC, device for converting digital signals to analog signals comprises a RF output for outputting the analog signals, a thermometer segment comprising a first number of data slices and a second number calibration slices, and a calibration controller, which electrically disconnects one of the data slices from the RF output and at the same time connects one of the calibration slices to the RF output as replacement slice for the respective data slice and performs a calibration of the disconnected data slice.

A built-in self-test (BIST) circuit is provided for testing an analog-to-digital converter (ADC). A multi-order sigma-delta (ΣΔ) modulator has an input that receives an input signal, a first output generating analog test signal derived from the input signal and applied to an input of the ADC and a second output generating a binary data stream. A digital recombination and filtering circuit has a first input that receives the binary data stream and a second input that receives a digital test signal output from the ADC in response to the analog test signal. The digital recombination and filtering circuit combines and filters the binary data stream and digital test signal to generate a digital result signal including a signal component derived from an error introduced by operation of the ADC. A correlation circuit is used to isolate that error signal component.

A method for calibrating a phase nonlinearity of a digital-to-time converter is provided. The method includes generating, based on a control word, a reference signal using a phase-locked loop. A frequency of the reference signal is equal to a frequency of an output signal of the digital-to-time converter. Further, the method includes measuring a temporal order of a transition of the output signal from a first signal level to a second signal level, and a transition of the reference signal from the first signal level to the second signal level. The method additionally includes adjusting a first entry of a look-up table based on the measured temporal order.

A built-in-self-test (BIST) circuit is connected to a processor and a sigma-delta modulator (SDM) and includes an averaging circuit, a reference signal generator, and a comparator. The averaging circuit calculates an average of a sum of a set of bit signals of the SDM output signal over a period of time period, and generates an average SDM signal. The reference signal generator generates a reference SDM signal based on an SDM input signal. The comparator compares the voltage levels of the average SDM and reference SDM signals with a threshold value, and generates a test output signal based on the comparison.

A method for removing low frequency offset components from a digital data stream includes receiving, at an input of an analog-to-digital converter (ADC), an analog input signal from one or more analog front end components. The analog input signal has an associated low frequency offset due, at least in part, to the analog front end components. The method also includes generating, at an output of the ADC, a digital data stream representative of the analog input signal. The digital data stream having an associated low frequency offset due, at least in part, to the analog front end components and the ADC. One or more low pass finite impulse response (FIR) filters are applied to the digital data stream to detect the low frequency offset components in the digital data stream, and generate a filtered output signal with only the low frequency offset components present. A corrected digital data stream without the low frequency offset components is generated in response thereto, for example, by taking the difference of the filtered output signal from the digital data stream.

The present disclosure relates to circuitry comprising: digital circuitry configured to generate a digital output signal; and monitoring circuitry configured to monitor a supply voltage to the digital circuitry and to output a control signal for controlling operation of the digital circuitry, wherein the control signal is based on the supply voltage.

A method of increasing SAR ADC conversion rate and reducing power consumption by employing a new timing scheme and minimizing timing delay for each bit-test during binary-search process. The high frequency clock input requirement is eliminated and higher speed rate can be achieved in SAR ADC.

An automated test equipment for analyzing an analog time domain output signal of an electronic device under test includes: an analog-to-digital converter configured for converting an analog time domain signal; a sampling clock configured for producing a clock signal; a time-to-frequency converter configured for converting the digital time domain signal into a digital frequency domain signal so that the digital frequency domain signal is represented by frequency bins; a memory device configured for storing a set of empirically determined operating parameters; and a jitter components removal module for removing jitter components produced by the analog-to-digital converter, wherein the jitter removal module is configured for subtracting the lower spur and the upper spur of each frequency bin of the frequency bins from the digital frequency domain signal so that the cleaned digital frequency domain signal is produced.